公开(公告)号：US11769820B2

公开(公告)日：2023-09-26

申请号：US16949446

申请日：2021-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/66545

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

公开(公告)号：US20230275153A1

公开(公告)日：2023-08-31

申请号：US18311016

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US11728344B2

公开(公告)日：2023-08-15

申请号：US16847116

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsieh Wong ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H10B10/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/7851 ,  H01L29/78696 ,  H10B10/12 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.

公开(公告)号：US20230253474A1

公开(公告)日：2023-08-10

申请号：US18300192

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/764 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L29/4991 ,  H01L29/66636 ,  H01L29/66545 ,  H01L21/764 ,  H01L29/6653 ,  H01L29/6656 ,  H01L21/02164 ,  H01L29/7851 ,  H01L21/31116 ,  H01L21/02167 ,  H01L29/0847 ,  H01L21/0217 ,  H01L29/66795

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

公开(公告)号：US11710792B2

公开(公告)日：2023-07-25

申请号：US17341088

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H10B10/00 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.

公开(公告)号：US11694933B2

公开(公告)日：2023-07-04

申请号：US16218330

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Yi-Hsiu Liu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.

公开(公告)号：US11677028B2

公开(公告)日：2023-06-13

申请号：US16923686

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/823814

Abstract: A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.

公开(公告)号：US11677027B2

公开(公告)日：2023-06-13

申请号：US17371953

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/66545

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US11647634B2

公开(公告)日：2023-05-09

申请号：US17018114

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H01L27/11 ,  H01L27/11597 ,  H01L29/78 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66

CPC classification number: H01L27/11597 ,  G11C5/06 ,  G11C11/223 ,  H01L21/8221 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US20230101134A1

公开(公告)日：2023-03-30

申请号：US17986451

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsin Yang ,  Yen-Ming Chen ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Dian-Hau Chen

IPC: H01L29/49 ,  G06F30/392 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.