公开(公告)号：US09875928B2

公开(公告)日：2018-01-23

申请号：US14682124

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

公开(公告)号：US09871138B2

公开(公告)日：2018-01-16

申请号：US15628658

申请日：2017-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US20180006129A1

公开(公告)日：2018-01-04

申请号：US15628592

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/516 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7869

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

公开(公告)号：US20170288018A1

公开(公告)日：2017-10-05

申请号：US15146898

申请日：2016-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/06 ,  H01L29/49 ,  H01L21/306 ,  H01L29/786 ,  H01L29/66 ,  H01L29/16 ,  H01L23/535

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/4975 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.

公开(公告)号：US09780165B2

公开(公告)日：2017-10-03

申请号：US15011683

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a plurality of fin-shaped structures thereon; forming a first shallow trench isolation (STI) between the fin-shaped structures and a second STI around the fin-shaped structures; removing part of the fin-shaped structures; and removing part of the first STI so that the top surfaces of the fin-shaped structures are higher than the top surface of the first STI and lower than the top surface of the second STI.

公开(公告)号：US09722080B2

公开(公告)日：2017-08-01

申请号：US14960444

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US09646849B2

公开(公告)日：2017-05-09

申请号：US14667823

申请日：2015-03-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the substrate, a first dielectric layer formed on the first capping layer; a second capping layer formed on the first dielectric layer; a second dielectric layer formed on the second capping layer; a plurality of conducting lines separately formed on the substrate; a third capping layer formed on the conducting lines and the second dielectric layer; and several nano-gaps formed between the adjacent conducting lines, and the nano-gaps being formed in the second dielectric layer, or further extending to the second capping layer or to the first capping layer. The nano-gaps partially open one of the second and first dielectric layers, or the nano-gaps expose the first capping layer or the second capping layer.

公开(公告)号：US20170077229A1

公开(公告)日：2017-03-16

申请号：US14876844

申请日：2015-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Yu-Cheng Tung ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.

Abstract translation: 本发明提供一种半导体结构，其包括具有第一导电区域和限定在其上的第二导电区域的基板，多个第一翅片结构和设置在基板上且在第一导电区域内的至少一个第一栅极结构，多个 的第二鳍结构和至少一个第二栅极结构，其设置在所述衬底上并且在所述第二导电区域内，设置在所述第一导电区域内的至少两个第一冠状外延层，设置在所述第二导电区域内的多个第二外延层，其中 第一冠状外延层的形状与第二外延层的形状不同。

公开(公告)号：US09583627B2

公开(公告)日：2017-02-28

申请号：US14793721

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有鳍状结构的基底，并且所述鳍状结构包括顶部和底部; 在鳍状结构上形成栅极结构; 在未被栅极结构覆盖的鳍状结构的顶部上形成盖层; 执行退火处理以将锗从盖层驱动到鳍状结构的顶部; 去除盖层; 以及围绕所述鳍状结构的顶部部分形成外延层。

公开(公告)号：US20170053980A1

公开(公告)日：2017-02-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.

Abstract translation: 制造单个扩散断裂的方法包括：提供具有与鳍片交叉的两个栅极结构的翅片和与鳍片交叉的中间伪栅极结构，其中中间伪栅极结构被栅极结构夹持。 之后，形成多个间隔物，并且每个间隔物分别围绕栅极结构和中间虚拟栅极结构。 然后，将中间的虚拟栅极结构和直接位于中间的虚拟栅极结构下面的鳍的一部分去除以形成凹部。 最后，形成凹部中的隔离层以封闭凹部的入口，以便形成嵌入凹槽内的空隙。