中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

389 records (took 0.02 seconds)

    OPTOELECTRONICS ASSEMBLY AND METHOD OF MAKING OPTOELECTRONICS ASSEMBLY
    121.
    发明申请
    OPTOELECTRONICS ASSEMBLY AND METHOD OF MAKING OPTOELECTRONICS ASSEMBLY 有权
    光电组件和制造光电组件的方法

    公开(公告)号：US20150060891A1

    公开(公告)日：2015-03-05

    申请号：US14013507

    申请日：2013-08-29

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： Yonggang Jin

    IPC: H01L31/173 ,  H01L23/00

    CPC classification number: H01L31/173 ,  H01L21/568 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L27/14678 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

    Abstract: An electronics assembly includes a semiconductor die assembly, an enclosure affixed to the semiconductor die assembly, the enclosure defining first and second chambers over the semiconductor die assembly, and first and second optical elements mounted in the first and second chambers, respectively. The semiconductor die assembly includes a semiconductor die encapsulated in a molded material, an encapsulation layer located on the top surface of the semiconductor die, and at least one patterned metal layer and at least one dielectric layer over the encapsulation layer. Conductive pillars extend through the encapsulation layer for electrical connection to the semiconductor die. The encapsulation layer blocks optical crosstalk between the first and second chambers. A method is provided for making the electronics assembly.

    Abstract translation: 电子组件包括半导体管芯组件，固定到半导体管芯组件的外壳，在半导体管芯组件上限定第一和第二腔室的外壳，以及安装在第一和第二腔室中的第一和第二光学元件。 半导体管芯组件包括封装在模制材料中的半导体管芯，位于半导体管芯的顶表面上的封装层，以及至少一个图案化金属层和封装层上的至少一个介电层。 导电柱延伸穿过封装层，以与半导体管芯电连接。 封装层阻止第一和第二腔室之间的光学串扰。 提供了一种用于制造电子组件的方法。

    Method for making paired lenses with an opaque barrier between, and product made
    122.
    发明授权
    Method for making paired lenses with an opaque barrier between, and product made 有权
    用于制造具有不透明屏障的成对透镜与制成的产品的方法

    公开(公告)号：US08937774B2

    公开(公告)日：2015-01-20

    申请号：US13657542

    申请日：2012-10-22

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： Laurent Herard

    IPC: G02B9/00

    CPC classification number: B29D11/00298 ,  G02B3/0031 ,  G02B3/0068 ,  G02B3/0075 ,  Y10T29/4998

    Abstract: A method comprises depositing an optical filter layer on a glass wafer, then cutting the wafer into dice. The dice are positioned on a carrier and encapsulated in a molding compound to form a reconstituted wafer, and the wafer is back-ground and polished. Lens faces are positioned on opposing surfaces of the glass dice and spacers are positioned on one side of the wafer. The wafer is then cut into lens modules, each having two side-by-side lenses with an opaque molding compound barrier between. The individual modules are attached to devices that require dual lenses, such as, e.g., proximity sensors that use a light source and a light receiver or detector.

    Abstract translation: 一种方法包括在玻璃晶片上沉积光学过滤层，然后将晶片切割成骰子。 将骰子定位在载体上并封装在模制化合物中以形成重构的晶片，并且将晶片进行背面和抛光。 透镜面定位在玻璃骰子的相对表面上，并且间隔物位于晶片的一侧。 然后将晶片切成透镜模块，每个透镜模块具有两个并排的透镜，其间具有不透明的模制化合物屏障。 各个模块附接到需要双透镜的装置，例如使用光源和光接收器或检测器的接近传感器。

    Camera module including an image sensor and a laterally adjacent surface mount device coupled at a lower surface of a dielectric material layer
    123.
    发明授权
    Camera module including an image sensor and a laterally adjacent surface mount device coupled at a lower surface of a dielectric material layer 有权
    相机模块包括耦合在介电材料层的下表面处的图像传感器和横向相邻的表面安装装置

    公开(公告)号：US08934052B2

    公开(公告)日：2015-01-13

    申请号：US12938235

    申请日：2010-11-02

    Applicant: Jing-En Luan

    Inventor： Jing-En Luan

    IPC: H04N5/225 ,  H01L31/0232 ,  H01L27/146

    CPC classification number: H04N5/2257 ,  H01L27/14618 ,  H01L31/02325 ,  H01L2924/0002 ,  H04N5/2251 ,  Y10T29/49002 ,  H01L2924/00

    Abstract: A low profile chip scale module and method of making of the same. The low profile chip scale module includes embedded SMD and integrated EM shielding. An adhesive layer is arranged on a substrate, e.g., chip carrier. Dies and SMDs are arranged on the adhesive layer. An etched frame and molding is attached to the substrate. Inputs/outputs (I/O) are formed and the substrate is coated with a dielectric material. Metal lines and connections among bond pads are formed and another layer of dielectric material is applied as a protective layer. The substrate is cut into various predetermined sizes and a lens is attached to form the chip scale module.

    Abstract translation: 一种低调的芯片规模模块及其制造方法。 低调芯片尺寸模块包括嵌入式SMD和集成EM屏蔽。 粘合剂层布置在基底上，例如芯片载体上。 模具和SMD布置在粘合剂层上。 将蚀刻的框架和模制件附接到基板。 形成输入/输出（I / O），并且用电介质材料涂覆基板。 形成金属线和接合焊盘之间的连接，另外施加介电材料层作为保护层。 将基板切割成各种预定尺寸，并且连接透镜以形成芯片刻度模块。

    Methods and devices for packaging integrated circuits
    124.
    发明授权
    Methods and devices for packaging integrated circuits 有权
    集成电路封装的方法和装置

    公开(公告)号：US08907465B2

    公开(公告)日：2014-12-09

    申请号：US13853645

    申请日：2013-03-29

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Wei Zhen Goh

    IPC: H01L23/02 ,  B81C1/00 ,  B81B7/00

    CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/00014

    Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

    Abstract translation: 集成电路封装的方法和装置。 封装的装置可以包括集成电路，包括图案化表面的第一包装部件和第二包装部件。 第一包装部件的图案化表面可以粘合地耦合到第二包装部件的表面或集成电路的表面。 集成电路可以至少部分地封装在第一和第二封装部件之间。 包装方法可以包括图案化集成电路封装的封装部件的表面。 包装部件的表面可以用于粘合地耦合到第二部件以至少部分地封装集成电路封装中的集成电路。

    MICROELECTRONIC ENVIRONMENTAL SENSING MODULE
    127.
    发明申请
    MICROELECTRONIC ENVIRONMENTAL SENSING MODULE 有权
    微电子环境感应模块

    公开(公告)号：US20140294046A1

    公开(公告)日：2014-10-02

    申请号：US13853801

    申请日：2013-03-29

    Applicant: STMICROELECTRONICS PTE LTD.

    Inventor： Olivier Le Neel ,  Ravi Shankar ,  Suman Cherian

    IPC: G01W1/02

    CPC classification number: G01W1/02 ,  G01F1/44 ,  G01P5/14

    Abstract: Sensors for air flow, temperature, pressure, and humidity are integrated onto a single semiconductor die within a miniaturized Venturi chamber to provide a microelectronic semiconductor-based environmental multi-sensor module that includes an air flow meter. One or more such multi-sensor modules can be used as building blocks in dedicated application-specific integrated circuits (ASICs) for use in environmental control appliances that rely on measurements of air flow. Furthermore, the sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. By integrating the Venturi chamber with accompanying environmental sensors, correction factors can be obtained and applied to compensate for temporal humidity fluctuations and spatial temperature variation using the Venturi apparatus.

    Abstract translation: 用于气流，温度，压力和湿度的传感器被集成到小型文丘里室内的单个半导体管芯上，以提供包括空气流量计的基于微电子半导体的环境多传感器模块。 一个或多个这样的多传感器模块可以用作专用于专用集成电路（ASIC）中的构件块，用于依赖于气流测量的环境控制设备。 此外，传感器模块可以建立在可用于处理来自传感器的信号的现有电路之上。 通过将文丘里腔室与随附的环境传感器集成，可以获得校正因子并应用于使用文丘里仪器来补偿时间湿度波动和空间温度变化。

    Window clamp top plate for integrated circuit packaging
    129.
    发明授权
    Window clamp top plate for integrated circuit packaging 有权
    窗夹板顶板用于集成电路封装

    公开(公告)号：US08796826B2

    公开(公告)日：2014-08-05

    申请号：US13335467

    申请日：2011-12-22

    Applicant: Xueren Zhang ,  Kim-Yong Goh ,  Wingshenq Wong

    Inventor： Xueren Zhang ,  Kim-Yong Goh ,  Wingshenq Wong

    IPC: H01L23/495 ,  H01L21/44 ,  B23K31/02 ,  B23K37/04

    CPC classification number: H01L24/78 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/14 ,  H01L2924/3025 ,  Y10T29/53265 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

    Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.

    Abstract translation: 一种用于在各种包装方法步骤期间最小化可能危及引线框安装件到集成电路管芯封装中的支撑结构的力的装置和方法。 当使用窗夹来在包装期间在引线框接合步骤期间或在引线接合步骤期间提供压力时，由窗夹具施加的垂直力可以通过支撑结构的顶板的物理轮廓在横向方向上传递 。 通过改变支撑结构的顶板的物理轮廓，例如通过设置特定类型的轮廓突起，可以最小化或消除作用于实现引线框架与支撑结构的牢固结合的侧向力。 此外，在引线接合期间，相同的最小化或消除侧向力导致改善的引线接合。

Patent Agency Ranking