公开(公告)号：US6136707A

公开(公告)日：2000-10-24

申请号：US410898

申请日：1999-10-02

申请人： Uri Cohen

发明人： Uri Cohen

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76873 ,  H01L2221/1089

摘要： One embodiment of the present invention is a method for making metallic interconnects including: (a) forming a patterned insulating layer on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) depositing a barrier layer over the field and inside surfaces of the at least one opening; (c) depositing a first seed layer over the barrier layer using a first deposition technique; (d) depositing a second seed layer over the first seed layer using a second deposition technique, the first and second deposition techniques being different; and (e) electroplating a metallic layer over the second seed layer, the electroplated metallic layer including a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals.

摘要翻译： 本发明的一个实施例是一种用于制造金属互连的方法，包括：（a）在衬底上形成图案化绝缘层，所述图案化绝缘层包括至少一个开口和围绕所述至少一个开口的场; （b）在所述至少一个开口的场和内表面上沉积阻挡层; （c）使用第一沉积技术在所述阻挡层上沉积第一籽晶层; （d）使用第二沉积技术在所述第一种子层上沉积第二种子层，所述第一和第二沉积技术是不同的; 和（e）在第二晶种层上电镀金属层，所述电镀金属层包括选自由Cu，Ag或包括这些金属中的一种或多种的合金组成的组的材料。

公开(公告)号：US11990368B2

公开(公告)日：2024-05-21

申请号：US17848162

申请日：2022-06-23

申请人： Applied Materials, Inc.

发明人： Mehul B. Naik ,  Zhiyuan Wu

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC分类号： H01L21/76849 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089

摘要： Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes forming a barrier layer on exposed surfaces of a feature in a dielectric layer, forming a liner layer on the barrier layer, forming a seed layer on the liner layer, forming a metal fill on the seed layer by a metal fill process and overburdening the feature using an electroplating process, performing a planarization process to expose a top surface of the dielectric layer, and selectively forming a cobalt-aluminum alloy cap layer on the barrier layer, the liner layer, the seed layer, and the metal fill by exposing the substrate to a cobalt-containing precursor and an aluminum-containing precursor.

公开(公告)号：US20190252244A1

公开(公告)日：2019-08-15

申请号：US15895512

申请日：2018-02-13

申请人： Raytheon Company

发明人： Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC分类号： H01L21/768 ,  H01L21/56 ,  H05K3/42 ,  C23C18/16 ,  H01L23/31 ,  H01L23/528 ,  C25D7/12

CPC分类号： H01L21/7684 ,  C23C18/1653 ,  C23C18/168 ,  C25D7/123 ,  H01L21/02065 ,  H01L21/568 ,  H01L21/76873 ,  H01L23/3121 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L2221/1089 ,  H01L2224/03009 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83896 ,  H05K3/424

摘要： A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

公开(公告)号：US09984975B2

公开(公告)日：2018-05-29

申请号：US14212890

申请日：2014-03-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Ching-Fu Yeh ,  Yu-Min Chang ,  You-Hua Chou ,  Chih-Wei Chang

IPC分类号： H01L21/4763 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

公开(公告)号：US09728502B2

公开(公告)日：2017-08-08

申请号：US14920867

申请日：2015-10-22

申请人： Samsung Electronics Co., Ltd.

发明人： Ganesh Hegde ,  Mark Rodder ,  Rwik Sengupta ,  Chris Bowen

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L2221/1089

摘要： A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.

公开(公告)号：US09673090B2

公开(公告)日：2017-06-06

申请号：US12471571

申请日：2009-05-26

申请人： Uri Cohen

发明人： Uri Cohen

IPC分类号： H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76873 ,  H01L2221/1089

摘要： One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) at least one of the PVD seed layers includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals, (iii) the PVD seed layers have no substantial overhangs sealing or pinching-off the top corners of the at least one opening, (iv) the combined thickness of the seed layers over the field is sufficient to enable uniform electroplating across the substrate, and (v) the combined seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening.

公开(公告)号：US20160133513A1

公开(公告)日：2016-05-12

申请号：US14920867

申请日：2015-10-22

申请人： Samsung Electronics Co., Ltd.

发明人： Ganesh HEGDE ,  Mark RODDER ,  Rwik SENGUPTA ,  Chris BOWEN

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L2221/1089

摘要： A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.

摘要翻译： 公开了一种用于形成金属 - 氧硅酸盐扩散屏障用于大马士革金属化的方法。 在层间电介质（ILD）材料中形成沟槽。 在沟槽中形成包含硅，碳，氧，ILD的组成成分或其组合的氧硅酸盐形成增强层。 在氧硅酸盐形成增强层上形成阻挡种子层，其包含选自第一组元素金属的元素金属和选自第二组元素金属的元素金属。 第二组中的元素金属在铜或其合金中是不混溶的，其扩散常数大于铜或其合金的自扩散; 在氧硅酸盐形成过程中不会降低硅 - 氧键; 并且促进铜或铜合金与金属 - 氧硅酸盐屏障扩散层的粘附。 然后将该结构退火以形成金属 - 氧硅酸盐扩散阻挡层。

公开(公告)号：US20160126134A1

公开(公告)日：2016-05-05

申请号：US14527692

申请日：2014-10-29

申请人： APPLIED Materials, Inc.

发明人： Roey Shaviv ,  Ismail T. Emesh

IPC分类号： H01L21/768 ,  C25D7/12

CPC分类号： H01L21/76873 ,  C23C14/5846 ,  C23C18/1653 ,  C25D5/34 ,  C25D7/123 ,  C25D17/001 ,  H01L21/02068 ,  H01L21/6723 ,  H01L21/76843 ,  H01L21/76861 ,  H01L2221/1089

摘要： An electrochemical deposition plating tool in accordance with one embodiment of the present disclosure includes one or more electrochemical deposition chambers and a hydrogen radical H* generation chamber.

摘要翻译： 根据本公开的一个实施方案的电化学沉积电镀工具包括一个或多个电化学沉积室和氢根H *生成室。

公开(公告)号：US20150348910A1

公开(公告)日：2015-12-03

申请号：US14822928

申请日：2015-08-11

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Harry D. Cox ,  Brian M. Erwin ,  John J. Garant ,  Ekta Misra ,  Nicholas A. Polomoff ,  Jennifer D. Schuler

IPC分类号： H01L23/532 ,  H01L23/528

CPC分类号： H01L23/53238 ,  C25D3/38 ,  C25D5/02 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure including a stack of conformal layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers including a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another with the first layer being in direct contact with the dielectric layer, and a conductive feature located directly on top of the fourth layer within the opening.

摘要翻译： 一种结构，其包括在电介质层的顶部和电介质层的开口内的共形层叠层，所述叠层包括第一层，第二层，第三层和第四层， 第一层与电介质层直接接触的另一层的顶部，以及直接位于开口内第四层顶部的导电特征。

公开(公告)号：US20150345045A1

公开(公告)日：2015-12-03

申请号：US14637316

申请日：2015-03-03

申请人： APPLIED Materials, Inc.

发明人： Roey Shaviv ,  Ismail T. Emesh ,  Dimitrios Argyris ,  Serdar Aksu

IPC分类号： C25D7/12 ,  H01L23/532 ,  H01L21/768 ,  C25D3/48 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  H01L23/528 ,  H01L21/288

CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： In accordance with one embodiment of the present disclosure, a method for depositing metal on a reactive metal film on a workpiece includes electrochemically depositing a metallization layer on a seed layer formed on a workpiece using a plating electrolyte having at least one plating metal ion, a pH range of about 1 to about 6, and applying a cathodic potential in the range of about −0.5 V to about −4 V. The workpiece includes a barrier layer disposed between the seed layer and a dielectric surface of the workpiece, the barrier layer including a first metal having a standard electrode potential more negative than 0 V and the seed layer including a second metal having a standard electrode potential more positive than 0 V.

摘要翻译： 根据本公开的一个实施例，用于在工件上的反应性金属膜上沉积金属的方法包括使用具有至少一个电镀金属离子的电镀电解质在形成在工件上的籽晶层上电化学沉积金属化层， pH范围为约1至约6，并施加约-0.5V至约-4V范围内的阴极电势。工件包括设置在种子层和工件的电介质表面之间的阻挡层，阻挡层 包括具有比0V更负的标准电极电势的第一金属，并且晶种层包括具有比0V更正的标准电极电位的第二金属。