公开(公告)号：US20240332151A1

公开(公告)日：2024-10-03

申请号：US18605841

申请日：2024-03-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee JUNG ,  ChangOh KIM

IPC: H01L23/498 ,  H01L21/32 ,  H01L21/48 ,  H01L23/00 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/32 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/552 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0652 ,  H01L2224/05005 ,  H01L2224/05025 ,  H01L2224/29005 ,  H01L2224/29021 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2924/3025

Abstract: An integrated package and a method for making the same are provided. The integrated package may include: a substate; a first electronic component mounted on the substrate; a first dielectric layer formed on the substrate and covering the first electric component, wherein the dielectric layer is made of photo imageable dielectric material; a first redistribution layer formed in the first dielectric layer, wherein the first redistribution layer includes a first vertical portion running through the first dielectric layer and a first lateral portion formed on a top surface of the first dielectric layer; a second electronic component mounted above the first dielectric layer and coupled with the lateral portion of the first redistribution layer; and a second dielectric layer formed above the first dielectric layer and covering the second electronic component.

公开(公告)号：US12107028B2

公开(公告)日：2024-10-01

申请号：US18305913

申请日：2023-04-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KyungOe Kim ,  Wagno Alves Braganca, Jr. ,  DongSam Park

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.

公开(公告)号：US20240321768A1

公开(公告)日：2024-09-26

申请号：US18188720

申请日：2023-03-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HeeYoun Kim

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/29 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6661 ,  H01L2224/16227 ,  H01L2924/186 ,  H01L2924/3025

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

公开(公告)号：US20240258246A1

公开(公告)日：2024-08-01

申请号：US18635819

申请日：2024-04-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongKook Shin ,  KyoWang Koo ,  HeeYoun Kim ,  SeongKuk Kim

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/4871 ,  H01L21/50 ,  H01L23/3121

Abstract: A semiconductor device has a substrate and first and second electrical component disposed over the substrate. A first metal bar is disposed over the substrate between the first electrical component and second electrical component. The first metal bar is formed by disposing a mask over a carrier. An opening is formed in the mask and a metal layer is sputtered over the mask. The mask is removed to leave the metal layer within the opening as the first metal bar. The first metal bar can be stored in a tape-and-reel.

公开(公告)号：US20240250062A1

公开(公告)日：2024-07-25

申请号：US18414500

申请日：2024-01-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee JUNG ,  ChangOh KIM ,  HeeSoo LEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/82 ,  H01L21/561 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3185 ,  H01L2224/24137 ,  H01L2224/245 ,  H01L2224/82005 ,  H01L2224/82103 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A method for making a semiconductor device is provided. The method includes: providing a semiconductor assembly comprising a first semiconductor die and a second semiconductor die, wherein a first interconnection structure is electrically coupled to the first semiconductor die and a second interconnection structure is electrically coupled to the second semiconductor die; depositing an encapsulant layer over the semiconductor assembly to encapsulate the first interconnection structure and the second interconnection structure, wherein the encapsulant layer comprises an additive activatable by laser; forming an interconnection channel in the encapsulant layer and activating the additive of the encapsulant layer in the interconnection channel as a seed layer by laser patterning, wherein the interconnection channel exposes and interconnects the first and the second interconnection structures; forming a conductive layer in the interconnection channel of the encapsulant layer; and forming an outer layer on the encapsulant layer to cover the conductive layer.

公开(公告)号：US20240234291A1

公开(公告)日：2024-07-11

申请号：US18150567

申请日：2023-01-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HyunSeok Park ,  KyoWang Koo ,  Sinjae Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/49877 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L25/16 ,  H01L24/16

Abstract: A semiconductor device has a one-layer interconnect substrate and electrical component disposed over a first surface of the interconnect substrate. The electrical components can be discrete electrical devices, IPDs, semiconductor die, semiconductor packages, surface mount devices, and RF components. An RDL with a graphene core shell is formed over a second surface of the interconnect substrate. The graphene core shell has a copper core and a graphene coating formed over the copper core. The RDL further has a matrix to embed the graphene core shell. The graphene core shells through RDL form an electrical path. The RDL can be thermoset material or polymer or composite epoxy type matrix. The graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. The RDL with graphene core shell is useful for electrical conductivity and electrical interconnect within an SIP.

公开(公告)号：US20240234229A1

公开(公告)日：2024-07-11

申请号：US18395641

申请日：2023-12-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JiEun KWON ,  KyoWang KOO ,  HyunYoung KIM ,  SooBin YOO

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L23/315 ,  H01L23/49811

Abstract: A method for making a semiconductor device using a double side molding technology is provided. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the second surface of the substrate is uneven; forming a coating on the second surface of the substrate such that a first surface of the coating, which is facing away from the second surface of the substrate, is even; mounting a first electronic component on the first surface of the substrate; and forming a first encapsulant on the first surface of the substrate to cover the first electronic component.

公开(公告)号：US12009314B2

公开(公告)日：2024-06-11

申请号：US17819271

申请日：2022-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YoungCheol Kim ,  ChoonHeung Lee ,  WonGyou Kim

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: A semiconductor device has a substrate and a plurality of bond wires is disposed in a pattern across on the substrate. The pattern of bond wires can be a plurality of rows of bond wires. A plurality of electrical components is disposed over the substrate as an SIP module. An encapsulant is deposited over the substrate, electrical components, and bond wire. An opening is formed in the encapsulant extending to the bond wire. The opening can be a trench extending across the bond wires disposed on the substrate, or a plurality of openings individually exposing each of a plurality of bond wires. A conductive material is disposed in the opening. A shielding layer is formed over the encapsulant and in contact with the conductive material. The shielding layer, conductive material, and bond wires reduce the effects of EMI, RFI, and other inter-device interference.

公开(公告)号：US11994801B2

公开(公告)日：2024-05-28

申请号：US17319785

申请日：2021-05-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Giwoong Nam ,  Junghwan Jang ,  Inhee Hwang ,  Taekyu Choi ,  Sanghyun Park

IPC: G03F7/16 ,  B05C11/06 ,  H01L21/02

CPC classification number: G03F7/168 ,  B05C11/06 ,  G03F7/162 ,  G03F7/164 ,  H01L21/0209

Abstract: A semiconductor manufacturing device has an outer cup and inner cup with a wafer suction mount disposed within the outer cup. A photoresist material is applied to a first surface of a semiconductor wafer disposed on the wafer suction mount while rotating at a first speed. A gas port is disposed on the inner cup for dispensing a gas oriented toward a bottom side of the semiconductor wafer. The gas port purges a second surface of the semiconductor wafer with a gas to remove contamination. The second surface of the semiconductor wafer is rinsed while purging with the gas. The gas can be a stable or inert gas, such as nitrogen. The contamination is removed from the second surface of the semiconductor wafer through an outlet between the inner cup and outer cup. The semiconductor wafer rotates at a second greater speed after discontinuing purge with the gas.

公开(公告)号：US20240096736A1

公开(公告)日：2024-03-21

申请号：US17932987

申请日：2022-09-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HyunSeok Park

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367 ,  H01L25/16

CPC classification number: H01L23/3733 ,  H01L21/4882 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3737 ,  H01L25/165 ,  H01L24/16

Abstract: A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.