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    2D self-aligned via first process flow
    131.
    发明授权
    2D self-aligned via first process flow 有权
    通过第一工艺流程进行二维自对准

    公开(公告)号：US09362165B1

    公开(公告)日：2016-06-07

    申请号：US14707443

    申请日：2015-05-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Andy Wei ,  Sudharshanan Raghunathan

    IPC: H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

    Abstract translation: 提供了在形成后续金属层之前形成2D自对准通孔并降低所得器件和所得器件的电容的方法。 实施例包括在SiOC层中形成虚拟金属线并沿第一方向延伸; 用金属线替代虚拟金属线，每条金属线都有氮化物盖; 在氮化物盖和SiOC层上形成软掩模堆叠; 通过所述软掩模堆叠将多个通孔图形化成金属线，所述多个通孔沿着第二方向自对准; 去除软掩码堆栈; 在金属线上形成第二虚拟金属线并在第二方向上延伸; 在SiOC层上的虚拟第二金属线之间形成第二SiOC层; 并且用第二金属线代替虚拟第二金属线，第二金属线通过通孔与金属线电连接。

    BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION
    133.
    发明申请
    BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION 有权
    通过金属收缩双重积分的无边界接触形式

    公开(公告)号：US20160064514A1

    公开(公告)日：2016-03-03

    申请号：US14469014

    申请日：2014-08-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

    IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

    Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

    Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

    Methods for fabricating integrated circuits using directed self-assembly
    134.
    发明授权
    Methods for fabricating integrated circuits using directed self-assembly 有权
    使用定向自组装制造集成电路的方法

    公开(公告)号：US09275896B2

    公开(公告)日：2016-03-01

    申请号：US14341985

    申请日：2014-07-28

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Deniz Elizabeth Civay ,  Ji Xu ,  Gerard Schmid ,  Guillaume Bouche ,  Richard A. Farrell

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

    CPC classification number: H01L21/76802 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897

    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

    Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用覆盖在半导体衬底上的蚀刻层的侧壁来形成引导限制阱的图形外延生成DSA。 使用嵌段共聚物填充指向封闭的石墨电极DSA。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 蚀刻相位被蚀刻，同时使耐腐蚀相位基本上到位以限定具有纳米图案的蚀刻掩模。 将纳米图案转移到蚀刻层。

    METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES
    136.
    发明申请
    METHODS OF FORMING NANOWIRE DEVICES WITH SPACERS AND THE RESULTING DEVICES 有权
    形成具有间隔器和结果器件的纳米器件的方法

    公开(公告)号：US20150372111A1

    公开(公告)日：2015-12-24

    申请号：US14308257

    申请日：2014-06-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

    IPC: H01L29/66 ,  H01L29/76

    CPC classification number: H01L29/66439 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/775

    Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

    Abstract translation: 形成纳米线器件的方法包括在半导体衬底之上形成半导体材料层，在半导体材料层之上形成栅极结构，形成与栅极结构相邻的第一侧壁间隔物，并形成邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括使半导体材料层图案化，使得每个层具有第一和第二暴露的端表面。 栅极结构，第一侧壁间隔件和第二侧壁间隔件在图案化工艺期间被组合用作蚀刻掩模。 该方法还包括去除第一和第二侧壁间隔物，从而暴露图案化的半导体材料层的至少一部分。 该方法还包括在除去第一和第二侧壁间隔物之后，在至少图案化的半导体材料层的暴露部分中形成掺杂的延伸区域。

    Integrated circuits with dual silicide contacts and methods for fabricating same
    137.
    发明授权
    Integrated circuits with dual silicide contacts and methods for fabricating same 有权
    具有双硅化物触点的集成电路及其制造方法

    公开(公告)号：US09196694B2

    公开(公告)日：2015-11-24

    申请号：US14043017

    申请日：2013-10-01

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

    IPC: H01L21/44 ,  H01L29/417 ,  H01L27/092

    CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

    Abstract: Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.

    Abstract translation: 提供了具有双硅化物触点的集成电路和用于制造具有双硅化物触点的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有PFET区域和NFET区域的半导体衬底。 该方法选择性地从PFET区域中的第一金属形成第一硅化物接触。 此外，该方法从NFET区域中的第二金属选择性地形成第二硅化物接触。 第二种金属与第一种金属不同。

    Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same
    138.
    发明授权
    Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same 有权
    具有金属绝缘体半导体（MIS）接触结构的集成电路及其制造方法

    公开(公告)号：US09177805B2

    公开(公告)日：2015-11-03

    申请号：US14166660

    申请日：2014-01-28

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

    IPC: H01L21/00 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

    Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。

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