公开(公告)号：US09570394B1

公开(公告)日：2017-02-14

申请号：US15140808

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/4763 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/32051 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: Embodiments of the present disclosure may provide methods of forming an IC structure with a pair of metal fins. An IC structure with a pair of metal fins can include two unitary metal fins positioned on a substrate and each including an elongated wire positioned on the substrate and a via positioned directly on a portion of the elongated wire, the elongated wire and the via of each unitary metal fin defining an inverted T-shape, wherein each unitary metal fin includes the elongated wire with a pair of opposing sidewalls substantially coplanar with a pair of opposing sidewalls of the via, and wherein the each unitary metal fin includes a single crystallographic orientation. An insulating layer can be positioned directly laterally between the two unitary metal fins.

Abstract translation: 本公开的实施例可以提供用一对金属翅片形成IC结构的方法。 具有一对金属翅片的IC结构可以包括位于基底上的两个单一金属翅片，每个包括位于基底上的细长线和直接位于细长线的一部分上的通孔，细长线和每个 一体式金属翅片限定了倒T形，其中每个单一金属翅片包括具有一对相对的侧壁的细长线，所述相对的侧壁与通孔的一对相对的侧壁基本共面，并且其中每个单一金属翅片包括单晶取向。 绝缘层可以直接横向放置在两个单一金属翅片之间。

公开(公告)号：US09553017B2

公开(公告)日：2017-01-24

申请号：US14729342

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76877 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括选择性地沉积覆盖金属化层的金属线的金属层，所述金属层设置在介电材料的ILD层中，而ILD层的与金属横向相邻的上表面 线暴露。 在ILD层的与金属层相邻的上表面上形成硬掩模层。 去除金属层以暴露金属线，同时使硬掩模层完好无损。 与硬掩模层相邻的金属线形成互连。

公开(公告)号：US09425280B2

公开(公告)日：2016-08-23

申请号：US14711196

申请日：2015-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/51

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

Abstract translation: 本文公开的一种方法包括形成邻近牺牲栅极结构的至少一个牺牲侧壁间隔物，所述牺牲栅极结构形成在半导体衬底上方，去除牺牲栅极结构的至少一部分，从而限定由牺牲隔离物横向限定的栅极腔， 在栅极腔中形成替代栅极结构，去除牺牲隔离物，从而限定邻近置换栅极结构的间隔空腔，并在间隔空腔中形成低k隔离物。 本文公开的新型器件包括位于半导体衬底上方的栅极结构，其中栅绝缘层具有相对于衬底的上表面基本上垂直取向的两个直立部分。 该装置还包括邻近栅极绝缘层的垂直取向的竖立部分的低k侧壁间隔件。

公开(公告)号：US09318436B2

公开(公告)日：2016-04-19

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US09236557B2

公开(公告)日：2016-01-12

申请号：US14156210

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Hyun-Jin Cho

IPC: H01L21/00 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L43/12

Abstract: Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MTJ between the metal layers using only one or two masks, the overall number of processing steps is reduced.

Abstract translation: 本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。 具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底部电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。 可选地，可以使用第二掩模对底部电极层进行图案化。 此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面 第一金属层。 通过仅使用一个或两个掩模在金属层之间形成MTJ，减少了处理步骤的总数。

公开(公告)号：US20150325467A1

公开(公告)日：2015-11-12

申请号：US14272787

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Kun Ho Ahn ,  Bernd Hintze ,  Frank Koschinsky

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用原子层沉积（ALD）工艺和物理气相沉积（PVD）工艺在半导体衬底上形成覆盖金属化层的金属线的势垒层。 将衬垫形成材料沉积在阻挡层上方以形成衬垫。 导电金属沉积在衬垫上方。

公开(公告)号：US09177858B1

公开(公告)日：2015-11-03

申请号：US14272787

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Kun Ho Ahn ,  Bernd Hintze ,  Frank Koschinsky

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用原子层沉积（ALD）工艺和物理气相沉积（PVD）工艺在半导体衬底上形成覆盖金属化层的金属线的势垒层。 将衬垫形成材料沉积在阻挡层上方以形成衬垫。 导电金属沉积在衬垫上方。

公开(公告)号：US09159617B2

公开(公告)日：2015-10-13

申请号：US14162841

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L21/20 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L29/456 ,  H01L21/02634 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET.

Abstract translation: 本发明的实施例提供半导体结构和形成半导体结构的方法。 半导体结构的实施例在基板上具有多个翅片。 半导体具有并且该方法实现了形成在并且基本上围绕形成在多个鳍片的顶部上的至少一个外延区域的硅化物层。 本发明的实施例提供了一种用于在外延区上形成保形硅化物层的方法和结构，其形成在finFET的未熔合翅片的顶部上。

公开(公告)号：US20150214105A1

公开(公告)日：2015-07-30

申请号：US14162841

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L29/456 ,  H01L21/02634 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET.

Abstract translation: 本发明的实施例提供半导体结构和形成半导体结构的方法。 半导体结构的实施例在基板上具有多个翅片。 半导体具有并且该方法实现了形成在并且基本上围绕形成在多个鳍片的顶部上的至少一个外延区域的硅化物层。 本发明的实施例提供了一种用于在外延区上形成保形硅化物层的方法和结构，其形成在finFET的未熔合翅片的顶部上。

公开(公告)号：US09093401B2

公开(公告)日：2015-07-28

申请号：US14473266

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: H01L21/3213 ,  H01L21/321 ,  H05K3/00 ,  H01L21/768 ,  H01L23/532 ,  H01L45/00 ,  C09G1/02 ,  H01L21/283 ,  H05K3/26

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。