公开(公告)号：US12218101B2

公开(公告)日：2025-02-04

申请号：US17697141

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

公开(公告)号：US12191162B2

公开(公告)日：2025-01-07

申请号：US17189006

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US12170275B2

公开(公告)日：2024-12-17

申请号：US17881519

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L23/522

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

公开(公告)号：US11990350B2

公开(公告)日：2024-05-21

申请号：US18106225

申请日：2023-02-06

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114

Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

公开(公告)号：US20240063184A1

公开(公告)日：2024-02-22

申请号：US17889914

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay ,  Bang-Ning Hsu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06551 ,  H01L2225/06586

Abstract: A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

公开(公告)号：US20240055366A1

公开(公告)日：2024-02-15

申请号：US17888324

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L24/96 ,  H01L24/94 ,  H01L24/32 ,  H01L25/0657 ,  H01L21/565 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L2224/95001 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2924/37001 ,  H01L2924/35121 ,  H01L2924/3511 ,  H01L2924/3025 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/06537 ,  H01L2924/182 ,  H01L2924/1811 ,  H01L2924/183 ,  H01L2924/186 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431

Abstract: A semiconductor device assembly, including a lower semiconductor die; a stack of upper semiconductor dies disposed over the lower semiconductor die; a conductive package perimeter material surrounding the stack of upper semiconductor dies; and an encapsulant material disposed between sidewalls of the stack of upper semiconductor dies and the conductive package perimeter material, and horizontally extending between the conductive package perimeter material and the lower semiconductor die. A method of forming a plurality of semiconductor assemblies, including stacking a plurality of semiconductor die stacks on a device wafer; disposing a pre-formed spacer assembly structure including a spacer material and a conductive package perimeter material around each of the plurality of semiconductor die stacks; disposing an encapsulant material between the conductive package perimeter material of the pre-formed spacer assembly structure and the corresponding semiconductor die stack; and singulating the device wafer to form the plurality of semiconductor device assemblies.

公开(公告)号：US20230307309A1

公开(公告)日：2023-09-28

申请号：US18200173

申请日：2023-05-22

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H05K7/20 ,  H01L23/42 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/36 ,  H05K7/2039 ,  H01L23/42 ,  H01L23/49822 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L25/0657 ,  H05K2201/10378 ,  H01L2225/1094 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/73204

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermal management layer disposed between the first and second devices. The thermal management layer may be configured to reduce heat transfer between the first and second devices.

公开(公告)号：US11735549B2

公开(公告)日：2023-08-22

申请号：US17376934

申请日：2021-07-15

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1146 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14517 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

公开(公告)号：US11710888B2

公开(公告)日：2023-07-25

申请号：US17543548

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01Q1/22 ,  H01L23/48 ,  H01L21/02

CPC classification number: H01Q1/2283 ,  H01L21/02104 ,  H01L23/481

Abstract: Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

公开(公告)号：US11652283B2

公开(公告)日：2023-05-16

申请号：US17392015

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01Q1/38 ,  H01L21/768 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01Q1/38 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5256

Abstract: Systems and methods of manufacture are disclosed for semiconductor device assemblies having a front side metallurgy portion, a substrate layer adjacent to the front side metallurgy portion, a plurality of through-silicon-vias (TSVs) in the substrate layer, metallic conductors located within at least a portion of the plurality of TSVs, and at least one conductive connection circuitry between the metallic conductors and the front side metallurgy portion. The plurality of TSVs with metallic conductors located within are configured to form an antenna structure. Selectively breakable connective circuitry is used to form and/or tune the antenna structure.