公开(公告)号：US12033699B2

公开(公告)日：2024-07-09

申请号：US17475424

申请日：2021-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Po-Kai Hsu

IPC: G11C16/04 ,  G06F7/544 ,  G11C16/08 ,  H03M1/12

CPC classification number: G11C16/04 ,  G06F7/5443 ,  G11C16/08 ,  H03M1/12

Abstract: A memory device and an operation method thereof are provided. The operation method comprises: in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of first signal lines; outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells; summing the cell currents on each of the second signal lines into a plurality of signal line currents: summing the signal line currents into a global signal line current: and converting the global signal line current into an output, wherein the output represents a MAC operation result of the inputs and the weights.

公开(公告)号：US11825653B2

公开(公告)日：2023-11-21

申请号：US16923144

申请日：2020-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H10B43/27 ,  H01L29/06 ,  H01L29/423 ,  H10B43/10 ,  H10B43/30 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: H10B43/27 ,  H01L29/0649 ,  H01L29/42344 ,  H10B43/10 ,  H10B43/30 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first portion and a second portion of the channel layer. The first portion is opposite to the second portion. The first portion is surrounded by the memory structure, and the second portion is exposed from the memory structure.

公开(公告)号：US20230368841A1

公开(公告)日：2023-11-16

申请号：US17742148

申请日：2022-05-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh ,  Chih-Chang Hsieh

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

公开(公告)号：US20230368821A1

公开(公告)日：2023-11-16

申请号：US18311800

申请日：2023-05-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chang Hsieh ,  Hang-Ting Lue

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/10 ,  G06F7/501

CPC classification number: G11C7/08 ,  G06F7/501 ,  G11C7/1096 ,  G11C7/12

Abstract: A memory device and a data approximation search method thereof are proposed. The memory device includes a plurality of selection switch pairs, a plurality of memory cell string pairs, a sense amplifier, and a page buffer. The selection switch pairs receive multiple search data pairs, respectively. The memory cell string pairs are respectively coupled to a global bit line through the selection switch pairs. Each of the memory cell string pairs determines whether to provide current on the global bit line according to stored data of a selected memory cell pair and each of the search data pairs. The sense amplifier obtains multiple search results according to the current on the global bit line and at least one reference currents respectively corresponding to at least one similarity. The page buffer records the search results and generates similarity information by accumulating the search results.

公开(公告)号：US11800697B2

公开(公告)日：2023-10-24

申请号：US17005550

申请日：2020-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H01L21/00 ,  H10B12/00 ,  G11C11/56 ,  G11C11/39 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B12/00 ,  G11C11/39 ,  G11C11/5621 ,  G11C11/5671 ,  H10B41/27 ,  H10B43/27

Abstract: A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.

公开(公告)号：US11710519B2

公开(公告)日：2023-07-25

申请号：US17368705

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Cheng-Lin Sung ,  Yung-Feng Lin

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/102 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US11678486B2

公开(公告)日：2023-06-13

申请号：US16784167

申请日：2020-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

公开(公告)号：US11605431B2

公开(公告)日：2023-03-14

申请号：US17325243

申请日：2021-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

公开(公告)号：US11476273B2

公开(公告)日：2022-10-18

申请号：US16924001

申请日：2020-07-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/417

Abstract: Provided are various three-dimensional flash memory devices. A three-dimensional flash memory device includes a gate stacked structure, separate arc-shaped channel pillars, source/drain pillars and a charge storage structure. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The arc-shaped channel pillar are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate and penetrate through the gate stacked structure, wherein two source/drain pillars are disposed at two ends of each of the arc-shaped channel pillars. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel pillar.

公开(公告)号：US20220130862A1

公开(公告)日：2022-04-28

申请号：US17077847

申请日：2020-10-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11556

Abstract: Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar.