公开(公告)号：US06465290B1

公开(公告)日：2002-10-15

申请号：US09818409

申请日：2001-03-27

申请人： Kyoichi Suguro ,  Kouji Matsuo ,  Atsushi Murakoshi ,  Yasuhiko Sato ,  Hiromi Niiyama

发明人： Kyoichi Suguro ,  Kouji Matsuo ,  Atsushi Murakoshi ,  Yasuhiko Sato ,  Hiromi Niiyama

IPC分类号： H01L21338

CPC分类号： H01L29/6659 ,  H01L29/66537 ,  H01L29/66545

摘要： Claimed and disclosed is a method of manufacturing a semiconductor device, the method comprising the steps of forming a dummy gate on a semiconductor substrate, forming a source-drain diffusion region by introducing an impurity into the semiconductor substrate having the dummy gate as a mask, removing the dummy gate to form an opening, and forming a gate electrode within the opening with a gate insulating film formed below the gate electrode. The dummy gate is further formed by coating the semiconductor substrate with a polymer having a higher carbon content than hydrogen content so as to form a polymer film, forming a photoresist pattern on the polymer film, and transferring the pattern shape of the photoresist pattern onto the polymer film.

摘要翻译： 权利要求和公开的是一种制造半导体器件的方法，所述方法包括以下步骤：在半导体衬底上形成虚拟栅极，通过将杂质引入到具有伪栅极的半导体衬底中作为掩模形成源极 - 漏极扩散区域， 去除所述虚拟栅极以形成开口，并且在所述开口内形成栅极电极，所述栅极绝缘膜形成在所述栅电极下方。 通过用具有比氢含量高的碳含量的聚合物涂覆半导体衬底以形成聚合物膜，在聚合物膜上形成光刻胶图案，并将光致抗蚀剂图案的图案形状转印到 聚合物膜。

公开(公告)号：US06376888B1

公开(公告)日：2002-04-23

申请号：US09559356

申请日：2000-04-27

申请人： Yoshitaka Tsunashima ,  Kyoichi Suguro ,  Atsushi Murakoshi ,  Kouji Matsuo ,  Toshihiko Iinuma

发明人： Yoshitaka Tsunashima ,  Kyoichi Suguro ,  Atsushi Murakoshi ,  Kouji Matsuo ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

摘要： Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the metal-containing film constituting at least a part of the second gate electrode and in contact with the second gate insulating film.

摘要翻译： 公开了一种半导体器件，其具有形成在第一区域中的N型MIS晶体管和形成在第二区域中的P型MIS晶体管，其中，所述N型MIS晶体管包括形成在至少底部的第一栅极绝缘膜 形成在所述第一区域中的第一凹部和形成在所述第一栅极绝缘膜上的第一栅电极，所述P型MIS晶体管包括形成在所述第二栅极绝缘膜的至少第二凹部的底部上的第二栅极绝缘膜， 区域和形成在所述第二栅极绝缘膜上的第二栅极电极，所述第一和第二栅极电极中的每一个包括至少一个含金属膜，并且所述第一和第二栅极电极中的至少一个是包括多个 的含金属膜的膜，并且构成第一栅电极的至少一部分并与第一栅极绝缘膜接触的含金属膜的功函数小于th 构成至少一部分第二栅电极并与第二栅极绝缘膜接触的含金属膜的功函数。

公开(公告)号：US06335534B1

公开(公告)日：2002-01-01

申请号：US09291967

申请日：1999-04-15

申请人： Kyoichi Suguro ,  Atsushi Murakoshi ,  Katsuya Okumura

发明人： Kyoichi Suguro ,  Atsushi Murakoshi ,  Katsuya Okumura

IPC分类号： H01J37317

CPC分类号： H01J37/3171 ,  H01J2237/31711

摘要： An electrically conductive mask having openings formed is located above a semiconductor substrate and ions are implanted into the surface of the semiconductor substrate through the electrically conductive mask, thereby forming ion implanted layers. For ion implantation under different conditions, a dedicated electrically conductive mask is used wit each ion implantation step.

摘要翻译： 具有形成开口的导电掩模位于半导体衬底之上，并且通过导电掩模将离子注入到半导体衬底的表面中，从而形成离子注入层。 对于在不同条件下的离子注入，每个离子注入步骤都使用专用的导电掩模。

公开(公告)号：US06239441B1

公开(公告)日：2001-05-29

申请号：US09007053

申请日：1998-01-14

申请人： Kyoichi Suguro ,  Katsuya Okumura

发明人： Kyoichi Suguro ,  Katsuya Okumura

IPC分类号： H01J37317

CPC分类号： H01L21/26593 ,  H01J37/3171 ,  H01L21/26513 ,  H01L21/324

摘要： The purpose of the present invention is to avoid a decrease in the mechanical strength of a Si substrate because of the repetition of ion-implantation and annealing processes. As ions are implanted while the Si substrate surface temperature is kept at as low as −60° C. or less. Then the Si substrate is heated to recover the implantation defects caused by the ion-implantation. Such a combination of the low temperature ion-implantation and the annealing processes is repeated as required.

摘要翻译： 本发明的目的是避免由于重复离子注入和退火过程而导致的Si衬底的机械强度降低。 当Si衬底表面温度保持在-60℃以下时，注入离子。 然后加热Si衬底以回收由离子注入引起的注入缺陷。 根据需要重复低温离子注入和退火处理的这种组合。

公开(公告)号：US6133150A

公开(公告)日：2000-10-17

申请号：US267376

申请日：1999-03-15

申请人： Kazuaki Nakajima ,  Yasushi Akasaka ,  Kiyotaka Miyano ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Yasushi Akasaka ,  Kiyotaka Miyano ,  Kyoichi Suguro

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/45 ,  H01L21/302

CPC分类号： H01L21/28247 ,  H01L21/76838 ,  H01L21/823835 ,  H01L29/456 ,  H01L2924/0002

摘要： A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.

摘要翻译： 半导体器件包括半导体衬底和绝缘地形成在半导体衬底上的层叠膜，其中层压膜包括半导体膜，在半导体膜上形成的难熔金属的金属膜，设置在金属膜之间的导电氧化防止膜 以及半导体膜，用于防止半导体膜在金属膜和半导体膜之间的界面中的氧化，以及形成在半导体膜的侧表面上并形成为延伸到半导体膜的上部和下部的氧化膜 在鸟的嘴形式。

公开(公告)号：US5989988A

公开(公告)日：1999-11-23

申请号：US192232

申请日：1998-11-16

申请人： Toshihiko Iinuma ,  Kyoichi Suguro ,  Soichi Nadahara

发明人： Toshihiko Iinuma ,  Kyoichi Suguro ,  Soichi Nadahara

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/76841 ,  H01L21/76883 ,  H01L29/665

摘要： A silicon region partitioned by insulating films is formed on a main surface of a substrate. A mixed film of first and second metals is formed directly or indirectly on the substrate having the silicon region formed thereon. Then, a heat treatment is applied to permit the first and second metals to react with silicon in the silicon region so as to form selectively a first silicide film on the surface of the silicon region. Further, the first silicide film is subjected to a heat treatment under a nitriding atmosphere so as to form a second silicide film consisting essentially of the first metal and silicon on the surface of the silicon region and a nitride film consisting essentially of the second metal and nitrogen on the surface of the second silicide film or both on the surface and at the crystal grain boundary of the second silicide film.

摘要翻译： 在基板的主表面上形成由绝缘膜分隔的硅区域。 直接或间接地在其上形成有硅区的基板上形成第一和第二金属的混合膜。 然后，进行热处理以允许第一和第二金属与硅区域中的硅反应，以在硅区域的表面上选择性地形成第一硅化物膜。 此外，第一硅化物膜在氮化气氛下进行热处理，以形成基本上由硅区域表面上的第一金属和硅组成的第二硅化物膜，以及基本上由第二金属和 第二硅化物膜的表面上的氮，或第二硅化物膜的表面上和晶界处的氮。

公开(公告)号：US5721175A

公开(公告)日：1998-02-24

申请号：US159953

申请日：1993-12-01

申请人： Iwao Kunishima ,  Kyoichi Suguro

发明人： Iwao Kunishima ,  Kyoichi Suguro

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/223

CPC分类号： H01L29/66575 ,  H01L21/28518 ,  H01L29/456 ,  Y10S148/019 ,  Y10S148/147

摘要： According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type, forming a transition metal compound layer containing a constituent element of the semiconductor substrate on the impurity diffusion layer, and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere. A semiconductor device includes a semiconductor substrate of a first conductivity type, an impurity diffusion layer of a second conductivity type formed in the semiconductor substrate of the first conductivity type, and a conductive metal compound layer formed on the impurity diffusion layer, wherein the conductive metal compound layer consists of at least a transition metal, a semiconductor element, and an impurity element of the second conductivity type which is an impurity element of the second conductivity type, and the impurity element of the second conductivity in the conductive metal compound layer is uniformly distributed.

摘要翻译： 根据本发明，制造半导体器件的方法包括以下步骤：在第一导电类型的半导体衬底上形成第二导电类型的杂质扩散层，形成含有半导体衬底的构成元素的过渡金属化合物层 在杂质扩散层上，通过在还原气氛中退火，在金属化合物层中掺杂第二导电类型的杂质。 半导体器件包括形成在第一导电类型的半导体衬底中的第一导电类型的半导体衬底，第二导电类型的杂质扩散层和形成在杂质扩散层上的导电金属化合物层，其中导电金属 复合层由至少一种过渡金属，半导体元件和作为第二导电类型的杂质元素的第二导电类型的杂质元素组成，并且导电金属化合物层中的第二导电性的杂质元素均匀 分散式。

公开(公告)号：US5640020A

公开(公告)日：1997-06-17

申请号：US713123

申请日：1996-09-16

申请人： Atsushi Murakoshi ,  Kyoichi Suguro ,  Tatsuya Hatanaka

发明人： Atsushi Murakoshi ,  Kyoichi Suguro ,  Tatsuya Hatanaka

IPC分类号： C23F4/00 ,  H01J27/02 ,  H01J27/08 ,  H01J27/14 ,  H01J27/16 ,  H01J27/18 ,  H01J37/08 ,  H01J37/317 ,  H01L21/265 ,  H01J3/02

CPC分类号： H01J37/32477 ,  H01J27/022 ,  H01J27/08 ,  H01J27/16 ,  H01J2237/08 ,  H01J2237/31701

摘要： An ion generation device includes a chamber in which plasma is generated, a first opening for introducing gas to be ionized by the plasma, and a second opening for irradiating ions generated from the gas. The inner wall of the chamber is coated with metal which is resistant to chemical etching by the ions and radicals.

公开(公告)号：US5424246A

公开(公告)日：1995-06-13

申请号：US99695

申请日：1993-07-30

申请人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

发明人： Mie Matsuo ,  Haruo Okano ,  Nobuo Hayasaka ,  Kyoichi Suguro ,  Hideshi Miyajima ,  Jun-ichi Wada

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532 ,  H01L21/205

CPC分类号： H01L21/76877 ,  H01L21/28518 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044

摘要： According to this invention, there is provided a method of forming a groove wiring layer, including the steps of forming a metal oxide film, consisting of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of a hydrogen oxide or of a carbon oxide, on an insulating film formed on a semiconductor substrate, and reducing the metal oxide film to form an electrode-wiring layer consisting of a metal which is a main component constituting the metal oxide. In this manner, an electrode-wiring layer having high EM and SM resistances without causing an increase in electric resistivity caused by an impurity or the like can be obtained.

摘要翻译： 根据本发明，提供一种形成沟槽布线层的方法，包括形成金属氧化物膜的步骤，该金属氧化物膜由标准自由能降低的金属氧化物组成，其小于氢的标准自由能的降低 氧化物或碳氧化物，在形成于半导体衬底上的绝缘膜上，还原金属氧化物膜，形成由作为构成金属氧化物的主要成分的金属构成的电极配线层。 以这种方式，可以获得具有高EM和SM电阻而不引起由杂质引起的电阻率增加的电极布线层等。

公开(公告)号：US5168332A

公开(公告)日：1992-12-01

申请号：US617793

申请日：1990-11-26

申请人： Iwao Kunishima ,  Tomonori Aoyama ,  Kyoichi Suguro

发明人： Iwao Kunishima ,  Tomonori Aoyama ,  Kyoichi Suguro

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L29/41 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/66272 ,  H01L21/2257 ,  H01L29/41 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66575 ,  Y10S148/019 ,  Y10S257/90

摘要： A semiconductor device including a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity type are selectively formed on the main top surface of the semiconductor substrate. The semiconductor device further includes metal compound layers consisting of constituting elements of the semiconductor substrate and a metal element. The metal compound layers are formed in the impurity diffusion layers in such a manner that they do not contact the insulative film, and the metal compound layers on the main back surface side of the semiconductor substrate have faces formed in parallel to the top surface of the semiconductor substrate.