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    CELL LAYOUTS
    143.
    发明公开
    CELL LAYOUTS 审中-公开

    公开(公告)号：US20230268335A1

    公开(公告)日：2023-08-24

    申请号：US17679655

    申请日：2022-02-24

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Juhan KIM ,  Sangmoon J. KIM ,  Mahbub RASHED ,  Navneet K. JAIN

    IPC: H01L27/02

    CPC classification number: H01L27/0207

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS
    145.
    发明公开
    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS 审中-公开

    公开(公告)号：US20230260561A1

    公开(公告)日：2023-08-17

    申请号：US17671652

    申请日：2022-02-15

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C11/22

    CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

    Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

    Self-aligned contact
    146.
    发明授权
    Self-aligned contact 有权

    公开(公告)号：US11721728B2

    公开(公告)日：2023-08-08

    申请号：US16777531

    申请日：2020-01-30

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Sipeng Gu ,  Jiehui Shu ,  Halting Wang ,  Yanping Shen

    IPC: H01L29/417 ,  H01L29/78

    CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/7851

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

    MULTIPLE-CORE HETEROGENEOUS WAVEGUIDE STRUCTURES INCLUDING MULTIPLE SLOTS
    148.
    发明公开
    MULTIPLE-CORE HETEROGENEOUS WAVEGUIDE STRUCTURES INCLUDING MULTIPLE SLOTS 审中-公开

    公开(公告)号：US20230244033A1

    公开(公告)日：2023-08-03

    申请号：US17588440

    申请日：2022-01-31

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Judson Holt

    IPC: G02B6/136

    CPC classification number: G02B6/136 ,  G02B2006/12061

    Abstract: Waveguide structures and methods of fabricating a waveguide structure. The structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material.

    SLOTTED SHIELDS FOR USE WITH AN ELECTRO-OPTICAL PHASE SHIFTER
    149.
    发明公开
    SLOTTED SHIELDS FOR USE WITH AN ELECTRO-OPTICAL PHASE SHIFTER 审中-公开

    公开(公告)号：US20230229028A1

    公开(公告)日：2023-07-20

    申请号：US18125165

    申请日：2023-03-23

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Kevin K. Dezfulian

    IPC: H01P5/04 ,  H01P1/18

    CPC classification number: H01P5/04 ,  H01P1/182

    Abstract: Structures including an electro-optical phase shifter and methods of fabricating a structure including an electro-optical phase shifter. The structure includes a waveguide core on a semiconductor substrate, and an interconnect structure over the waveguide core and the semiconductor substrate. The waveguide core includes a phase shifter, and the interconnect structure includes a slotted shield and a transmission line coupled to the phase shifter. The slotted shield includes segments that are separated by slots. The slotted shield is positioned between the transmission line and the substrate.

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