公开(公告)号：US20240295691A1

公开(公告)日：2024-09-05

申请号：US18622867

申请日：2024-03-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12 ,  H01L23/00

CPC classification number: G02B6/12002 ,  H01L24/32 ,  H01L2224/32225

Abstract: A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.

公开(公告)号：US12080630B2

公开(公告)日：2024-09-03

申请号：US18534433

申请日：2023-12-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L27/0623 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H10B63/30 ,  H10B63/845

Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.

公开(公告)号：US20240274534A1

公开(公告)日：2024-08-15

申请号：US18622992

申请日：2024-03-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.

公开(公告)号：US20240260262A1

公开(公告)日：2024-08-01

申请号：US18594804

申请日：2024-03-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B41/27 ,  G11C16/04 ,  H10B12/00 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B63/00

CPC classification number: H10B41/27 ,  G11C16/0483 ,  H10B12/20 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B63/84

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a plurality of second transistors disposed atop the second metal layer, a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one In-Out interface controller circuit.

公开(公告)号：US12051674B2

公开(公告)日：2024-07-30

申请号：US18604695

申请日：2024-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/10 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/66621 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351

Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.

公开(公告)号：US20240250163A1

公开(公告)日：2024-07-25

申请号：US18429202

申请日：2024-01-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B63/00 ,  H10B69/00

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

公开(公告)号：US12041791B2

公开(公告)日：2024-07-16

申请号：US18431177

申请日：2024-02-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145

Abstract: A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.

公开(公告)号：US20240222368A1

公开(公告)日：2024-07-04

申请号：US18603526

申请日：2024-03-13

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/268 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L24/73 ,  H01L27/088 ,  H01L29/66545 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

公开(公告)号：US20240222333A1

公开(公告)日：2024-07-04

申请号：US18604695

申请日：2024-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/66621 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351

Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.

公开(公告)号：US12021028B2

公开(公告)日：2024-06-25

申请号：US18389582

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B10/00 ,  H10B12/00 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B10/125 ,  H10B12/37 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L2225/06541

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.