公开(公告)号：US06548393B1

公开(公告)日：2003-04-15

申请号：US09927216

申请日：2001-08-10

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/78301 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48

Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, an insulative adhesive and a hardened connection joint. The conductive trace includes first and second opposing surfaces and a peripheral sidewall between the surfaces, the first surface faces away from the pad and the peripheral sidewall overlaps the pad. The adhesive is between the second surface and the pad. The connection joint contacts the first surface, the peripheral sidewall and the pad, extends between the peripheral sidewall and the pad and electrically connects the conductive trace and the pad. Preferably, the connection joint is reflowed solder or cured conductive adhesive. A method of manufacturing the assembly includes disposing the adhesive between the conductive trace and the pad, then etching the adhesive thereby exposing the pad, then depositing a non-solidified material on the first surface, the peripheral sidewall and the pad, and then transforming the non-solidified material into the connection joint.

Abstract translation: 半导体芯片组件包括半导体芯片，导电迹线，绝缘粘合剂和硬化连接接头。 导电迹线包括第一和第二相对表面以及表面之间的周边侧壁，第一表面背离焊盘并且周边侧壁与焊盘重叠。 粘合剂位于第二表面和垫之间。 连接接头接触第一表面，周边侧壁和垫，在周边侧壁和焊盘之间延伸，并且电连接导电迹线和焊盘。 优选地，连接接头是回焊焊料或固化的导电粘合剂。 制造组件的方法包括将粘合剂设置在导电迹线和焊盘之间，然后蚀刻粘合剂，从而暴露焊盘，然后在第一表面，外围侧壁和焊盘上沉积非固化材料，然后将 非固化材料进入连接接头。

公开(公告)号：US06511865B1

公开(公告)日：2003-01-28

申请号：US09864773

申请日：2001-05-24

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2148

CPC classification number: H01L23/49811 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2224/48 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes a conductive trace. A ball bond contacts and electrically connects the conductive trace and the pad. A method of manufacturing the assembly includes mechanically attaching the chip to the support circuit and then forming the ball bond using thermocompression or thermosonic wire bonding.

Abstract translation: 半导体芯片组件包括附接到支撑电路的半导体芯片。 支撑电路包括导电迹线。 球接触接触并电连接导电迹线和焊盘。 制造组件的方法包括将芯片机械地附接到支撑电路，然后使用热压或热超声线焊接形成球接合。

公开(公告)号：US06509639B1

公开(公告)日：2003-01-21

申请号：US10137071

申请日：2002-04-30

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2302

CPC classification number: H01L25/0657 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.

公开(公告)号：US06406939B1

公开(公告)日：2002-06-18

申请号：US09852822

申请日：2001-05-10

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/82 ,  H01L21/486 ,  H01L24/24 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/16225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/76155 ,  H01L2224/8201 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/83194 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching a chip to a substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the chip. The via holes are aligned with and placed on top of the pads so that the pads are exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the pads and the traces. Electrically conductive materials include electroless plated metals, electrochemical plated metals, solders, epoxies and conductive polymers.

Abstract translation: 倒装芯片组件及其形成方法，包括其中通孔用作半导体芯片和衬底之间的连接的单层或多层衬底。 组装步骤包括将芯片附接到具有多个通孔的衬底，用于将衬底上的各个迹线与芯片的相应输入/输出端子焊盘连接。 通孔与焊盘的顶部对齐并放置在焊盘的顶部，使得焊盘通过衬底的相对侧露出。 随后将导电材料沉积在通孔以及焊盘的表面上，以提供焊盘和迹线之间的电连接。 导电材料包括无电镀金属，电化学电镀金属，焊料，环氧树脂和导电聚合物。

公开(公告)号：US5830533A

公开(公告)日：1998-11-03

申请号：US985663

申请日：1992-12-04

Applicant: Charles W. C. Lin ,  Randy L. German

Inventor： Charles W. C. Lin ,  Randy L. German

IPC: H05K3/18 ,  B05D1/32

CPC classification number: H05K3/182 ,  H01L2224/02333

Abstract: A method of selectively fabricating metallization on a dielectric substrate is disclosed. A seed layer is sputtered on a polymer dielectric, a patterned photoresist mask is disposed over the seed layer, exposed portions of the seed layer are etched, the photoresist is stripped, and copper is deposited without a mask by electroless plating on the unetched seed layer to form well-adhering high density copper lines without exposing the photoresist to the electroless bath.

Abstract translation: 公开了一种在电介质基片上选择性地制造金属化的方法。 将种子层溅射在聚合物电介质上，将图案化的光致抗蚀剂掩模设置在种子层上，蚀刻种子层的暴露部分，剥离光致抗蚀剂，并且通过在未蚀刻的种子层上进行化学镀而不用掩模沉积铜 以形成良好粘附的高密度铜线，而不将光致抗蚀剂暴露于无电镀浴。

公开(公告)号：US5271822A

公开(公告)日：1993-12-21

申请号：US34027

申请日：1993-03-22

Applicant: Ernest R. Nolan ,  Charles W. C. Lin

Inventor： Ernest R. Nolan ,  Charles W. C. Lin

IPC: C25D7/12 ,  H05K3/24 ,  H05K3/34 ,  H05K13/04 ,  C25D5/02

CPC classification number: C25D7/12 ,  C25D17/004 ,  H05K13/0465 ,  H05K3/241 ,  H05K3/3473

Abstract: A method for selectively electroplating a metallic coating, such as solder, onto a plurality of small and closely spaced electrical contacts. The method includes sealingly enclosing the contacts in an electroplating cell having an anode, a cathode and a chamber, forming an electrical connection between the cathode and the contacts and electroplating the contacts.

Abstract translation: 一种用于选择性地将诸如焊料的金属涂层电镀到多个小且紧密间隔的电触点上的方法。 该方法包括将触点密封地封装在具有阳极，阴极和室的电镀单元中，在阴极和触点之间形成电连接并电镀触点。

公开(公告)号：US5223110A

公开(公告)日：1993-06-29

申请号：US805131

申请日：1991-12-11

Applicant: Ernest R. Nolan ,  Charles W. C. Lin

Inventor： Ernest R. Nolan ,  Charles W. C. Lin

IPC: C25D7/12 ,  H05K3/24 ,  H05K3/34 ,  H05K13/04

CPC classification number: C25D7/12 ,  C25D17/004 ,  H05K13/0465 ,  H05K3/241 ,  H05K3/3473

Abstract: A method and apparatus for selectively electroplating a metallic coating, such as solder, onto a plurality of small and closely spaced electrical contacts. The method includes sealingly enclosing the contacts in an electroplating cell having an anode, a cathode and a chamber, forming an electrical connection between the cathode and the contacts and electroplating the contacts.

Abstract translation: 一种用于选择性地将诸如焊料的金属涂层电镀到多个小且紧密间隔的电触点上的方法和装置。 该方法包括将触点密封地封装在具有阳极，阴极和室的电镀单元中，在阴极和触点之间形成电连接并电镀触点。

公开(公告)号：US5084299A

公开(公告)日：1992-01-28

申请号：US600361

申请日：1990-10-19

Applicant: Tom J. Hirsch ,  Charles W. C. Lin ,  Ian Y. K. Yee

Inventor： Tom J. Hirsch ,  Charles W. C. Lin ,  Ian Y. K. Yee

IPC: C23C18/16 ,  H05K3/18 ,  B05D3/06 ,  B05D5/12 ,  H01L21/312

CPC classification number: C23C18/1608 ,  C23C18/1612 ,  C23C18/204 ,  C23C18/208 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/32 ,  C23C18/38 ,  C23C18/42 ,  H05K3/185 ,  C23C18/2006 ,  H01L2924/00013 ,  H05K2203/107

Abstract: A method for patterning electroless plated metal on a polymer substrate. In a first embodiment a substrate is first coated with a polymer suitable for complexing a seed metal which can initiate electroless plating. The polymer is then mixed with a seed metal such as palladium, selectively irradiated to form the desired conductor pattern, and then etched so that the desired pattern remains. The substrate is subsequently placed in an electroless plating bath to form a metal pattern. In a second embodiment, before applying the seed metal a substrate immersed in a polymer solution suitable for complexing a seed metal can be selectively irradiated to selectively deposit polymer on the substrate, followed by applying a seed metal to form a polymer-seed metal mixture and an electroless plating bath. In addition, an alkaline chemical may be added to an acidic polymer to prevent the polymer from etching metal on the substrate.

Abstract translation: 一种在聚合物基材上构图化学镀金属的方法。 在第一实施方案中，首先用适于络合可以引发化学镀的种子金属的聚合物涂覆基材。 然后将聚合物与种子金属如钯混合，选择性地照射以形成所需的导体图案，然后进行蚀刻，使得所需图案保留。 然后将衬底放置在化学镀浴中以形成金属图案。 在第二实施例中，在施加种子金属之前，可以选择性地照射浸渍在适合于种子金属络合的聚合物溶液中的基底以选择性地沉积在基底上的聚合物，然后施加种子金属以形成聚合物种子金属混合物， 化学镀浴。 此外，可以向酸性聚合物中加入碱性化学物质以防止聚合物在基材上蚀刻金属。