公开(公告)号：US10014710B2

公开(公告)日：2018-07-03

申请号：US14964466

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Mark A. Schaecher ,  Teong Guan Yew ,  Eng Huat Goh

IPC: H02J7/02 ,  H02J50/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H02J7/025 ,  H01F27/36 ,  H01F38/14 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/18 ,  H01L25/50 ,  H02J50/10

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

公开(公告)号：US20180138146A1

公开(公告)日：2018-05-17

申请号：US15354291

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Min Suet Lim ,  Jackson Chung Peng Kong

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07001 ,  H01L2924/07025 ,  H01L2924/0675 ,  H01L2924/00014

Abstract: A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.

公开(公告)号：US09839134B2

公开(公告)日：2017-12-05

申请号：US14978264

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Bok Eng Cheah

IPC: H05K1/00 ,  H05K1/18 ,  H01Q1/38

CPC classification number: H05K1/189 ,  H01L24/19 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01Q1/2291 ,  H01Q1/38 ,  H01Q9/285 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/0154 ,  H05K2201/10098 ,  H05K2203/1469

Abstract: A flexible integrated circuit that includes a first dielectric layer having a first section at one polarity and a second section at an opposing polarity, wherein the first section and the second section are separated by dielectric material within first dielectric layer; a second dielectric layer having a first side wall that is electrically connected to the first section and a second side wall that is electrically connected to the second section; and a third dielectric layer having a base that is electrically connected to the first side wall and the second side wall, wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer, wherein the base, the first and second side walls and the first and second sections form an antenna that is configured to send or receive wireless signals.

公开(公告)号：US09812422B2

公开(公告)日：2017-11-07

申请号：US15273549

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Toong Erh Ooi ,  Bok Eng Cheah ,  Nitesh Nimkar

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L23/50 ,  H01L21/48 ,  H05K3/46 ,  H05K1/18

CPC classification number: H01L24/82 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/82345 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.

公开(公告)号：US20170012020A1

公开(公告)日：2017-01-12

申请号：US15273549

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Toong Erh Ooi ,  Bok Eng Cheah ,  Nitesh Nimkar

IPC: H01L23/00 ,  H01L21/48

CPC classification number: H01L24/82 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/82345 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.

Abstract translation: 一种包括模具的设备; 以及堆叠载体，其包括设置在所述管芯的器件侧上的交替的导电材料层和介电材料层，以及包埋所述管芯的厚度尺寸的一部分的电介质材料; 以及多个载体接触点，其设置在所述管芯的器件侧和所述管芯的嵌入的厚度尺寸之间的灰度处，并且被配置为将所述载体连接到衬底。 一种方法，包括在牺牲衬底上设置管芯，其中模具的器件侧与牺牲衬底相对; 在模具的器件侧附近形成堆积载体，其中所述积聚载体包括在所述管芯的器件侧和所述管芯的背面之间限定灰度的介电材料，所述等级包括多个载体接触点 ; 以及将所述管芯和所述载体与所述牺牲衬底分离。

公开(公告)号：US20160380386A1

公开(公告)日：2016-12-29

申请号：US14750846

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Kuan-Yu Chen ,  Bok Eng Cheah ,  Boon Ping Koh ,  Min Keen Tang ,  Howard L. Heck ,  Kooi Chi Ooi

IPC: H01R13/648 ,  H01R13/42

CPC classification number: H01R13/6485 ,  H05K9/0067

Abstract: In one example an electronic device comprises a housing, a receptacle in the housing comprising an opening at a distal end to receive a plug, a data connector positioned in the receptacle to provide a communication connection, and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly comprises a dedicated discharge path and a conductive pin mounted on a retention latch and moveable between a first position in which the conductive pin is in electrical contact with the data connector and a second position in which the conductive pin is not in electrical contact with the data connector. Other examples may be described.

Abstract translation: 在一个示例中，电子设备包括壳体，壳体中的插座，包括在远端处的接收插头的开口，位于插座中的数据连接器以提供通信连接，以及定位在开口附近的静电导体组件 插座，其中所述静电导体组件包括专用放电路径和安装在保持闩锁上的导电针，并且可在所述导电针与所述数据连接器电接触的第一位置和在所述第二位置之间移动的第二位置， 不与数据连接器电接触。 可以描述其他示例。

公开(公告)号：US12218064B2

公开(公告)日：2025-02-04

申请号：US17631254

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

Abstract: Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.

公开(公告)号：US20240395722A1

公开(公告)日：2024-11-28

申请号：US18789993

申请日：2024-07-31

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US12142570B2

公开(公告)日：2024-11-12

申请号：US17975223

申请日：2022-10-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US12112997B2

公开(公告)日：2024-10-08

申请号：US18216040

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/09 ,  H01L24/17 ,  H01L25/16 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.