公开(公告)号：US20240168878A1

公开(公告)日：2024-05-23

申请号：US18386746

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

公开(公告)号：US11960722B2

公开(公告)日：2024-04-16

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20240062799A1

公开(公告)日：2024-02-22

申请号：US17890040

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Akira Goda ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Tomoharu Tanaka ,  Eric N. Lee ,  Dung V. Nguyen ,  David Ebsen

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/4085

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

公开(公告)号：US20240028200A1

公开(公告)日：2024-01-25

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20230360705A1

公开(公告)日：2023-11-09

申请号：US18138551

申请日：2023-04-24

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Giovanni Maria Paolucci ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Akira Goda

IPC: G11C16/12 ,  G11C16/08

CPC classification number: G11C16/12 ,  G11C16/08

Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

公开(公告)号：US11805653B2

公开(公告)日：2023-10-31

申请号：US17145131

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H10B43/40 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B43/40 ,  G11C16/08 ,  H01L23/5329 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US20230335201A1

公开(公告)日：2023-10-19

申请号：US18135915

申请日：2023-04-18

Applicant: Micron Technology, Inc.

Inventor： Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  David Scott Ebsen ,  Dung Viet Nguyen ,  Akira Goda

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/08

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

公开(公告)号：US20230289062A1

公开(公告)日：2023-09-14

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US11710724B2

公开(公告)日：2023-07-25

申请号：US17649022

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/768 ,  H01L23/481 ,  H01L23/4827 ,  H01L24/05 ,  H01L25/50

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US11626162B2

公开(公告)日：2023-04-11

申请号：US16744675

申请日：2020-01-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Akira Goda ,  Peter Sean Feeley

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.