公开(公告)号：US20140009991A1

公开(公告)日：2014-01-09

申请号：US13972455

申请日：2013-08-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gurtej S. Sandhu

IPC: G11C13/00

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

公开(公告)号：US20130320440A1

公开(公告)日：2013-12-05

申请号：US13959339

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Venkatesan Ananthan

IPC: H01L29/78

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7827 ,  H01L29/7841

Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

Abstract translation: 本发明包括含有U形半导体材料片的浮体晶体管结构。 U形有一对连接到中心部分的插脚。 每个插脚包含一对门控耦合的源极/漏极区域的源极/漏极区域，并且晶体管的浮体在中心部分内。 半导体材料切片可以位于前门和后门之间。 可以将浮体晶体管结构并入到存储器阵列中，这又可以并入到电子系统中。 本发明还包括形成浮体晶体管结构的方法，以及将浮体晶体管结构结合到存储器阵列中的方法。

公开(公告)号：US20130292752A1

公开(公告)日：2013-11-07

申请号：US13938973

申请日：2013-07-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/108

CPC classification number: H01L21/762 ,  H01L21/32 ,  H01L27/0814 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/2454 ,  H01L27/2472 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

公开(公告)号：US20130221318A1

公开(公告)日：2013-08-29

申请号：US13856561

申请日：2013-04-04

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

公开(公告)号：US20250118653A1

公开(公告)日：2025-04-10

申请号：US18981288

申请日：2024-12-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending extend farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US12219765B2

公开(公告)日：2025-02-04

申请号：US18209173

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/06 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/50 ,  H10B63/00 ,  H10N70/20

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US20250022955A1

公开(公告)日：2025-01-16

申请号：US18904444

申请日：2024-10-02

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Hong Li ,  Erica L. Poelstra

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L23/49 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H10B12/00 ,  H10B63/00

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

公开(公告)号：US12142680B2

公开(公告)日：2024-11-12

申请号：US17317636

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Hong Li ,  Erica L. Poelstra

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/49 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H10B12/00 ,  H10B63/00 ,  H01L21/764

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

公开(公告)号：US20240365538A1

公开(公告)日：2024-10-31

申请号：US18765605

申请日：2024-07-08

Applicant: Micron Technology, Inc.

Inventor： Hong Li ,  Ramaswamy Ishwar Venkatanarayanan ,  Sanh D. Tang ,  Erica L. Poelstra

IPC: H10B12/00 ,  G11C11/402 ,  H01L23/49 ,  H01L23/538 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B12/488 ,  G11C11/4023 ,  H01L23/49 ,  H01L23/538 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/053 ,  H10B12/30 ,  H10B12/31 ,  H10B12/315 ,  H10B12/34

Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

公开(公告)号：US12069852B2

公开(公告)日：2024-08-20

申请号：US17862659

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Hong Li ,  Ramaswamy Ishwar Venkatanarayanan ,  Sanh D. Tang ,  Erica L. Poelstra

IPC: H10B12/00 ,  G11C11/402 ,  H01L23/49 ,  H01L23/538 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B12/488 ,  G11C11/4023 ,  H01L23/49 ,  H01L23/538 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/053 ,  H10B12/30 ,  H10B12/31 ,  H10B12/315 ,  H10B12/34

Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.