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    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    141.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20150287472A1

    公开(公告)日：2015-10-08

    申请号：US14746416

    申请日：2015-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/32 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

    Circuit Structures, Memory Circuitry, And Methods
    143.
    发明申请
    Circuit Structures, Memory Circuitry, And Methods 有权
    电路结构，存储器电路和方法

    公开(公告)号：US20140273358A1

    公开(公告)日：2014-09-18

    申请号：US14287659

    申请日：2014-05-27

    Applicant: Micron Technology, Inc.

    Inventor： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

    IPC: H01L29/66 ,  H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

    Abstract translation: 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

    Devices including channel materials and passivation materials
    145.
    发明授权
    Devices including channel materials and passivation materials 有权

    公开(公告)号：US12283636B2

    公开(公告)日：2025-04-22

    申请号：US18669237

    申请日：2024-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu

    IPC: H01L29/786 ,  H01L29/66

    Abstract: A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

    Memory array and methods used in forming a memory array
    146.
    发明授权
    Memory array and methods used in forming a memory array 有权

    公开(公告)号：US12274056B2

    公开(公告)日：2025-04-08

    申请号：US18433863

    申请日：2024-02-06

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Guangyu Huang ,  Haitao Liu

    IPC: H10B41/27 ,  G11C5/06 ,  H10B41/35 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

    Memory device having 2-transistor memory cell and access line plate
    147.
    发明授权
    Memory device having 2-transistor memory cell and access line plate 有权

    公开(公告)号：US12266660B2

    公开(公告)日：2025-04-01

    申请号：US18400082

    申请日：2023-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/788

    Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

    MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SHARED READ AND WRITE CONTROL GATES
    149.
    发明申请
    MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SHARED READ AND WRITE CONTROL GATES 有权

    公开(公告)号：US20240389329A1

    公开(公告)日：2024-11-21

    申请号：US18666358

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Albert Fayrushin ,  Haitao Liu ,  Kamal M. Karda

    IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory device, which includes a first memory cell string, a second memory cell string adjacent the first memory cell string, and a control gate. The first memory string includes a first channel structure, a first charge storage structure, and a first dielectric structure between the first channel structure and the first charge storage structure. The second memory cell string includes a second channel structure, a second charge storage structure, and a second dielectric structure between the second channel structure and the second charge storage structure. The control gate is separated from the first charge storage structure by a third dielectric structure and separated from the second channel structure by a fourth dielectric structure. The control gate and the first charge storage structure are between the first channel structure and the second channel structure.

    VERTICAL 2-TRANSISTOR MEMORY CELL
    150.
    发明申请
    VERTICAL 2-TRANSISTOR MEMORY CELL 有权

    公开(公告)号：US20240373619A1

    公开(公告)日：2024-11-07

    申请号：US18662659

    申请日：2024-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Srinivas Pulugurtha ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

    IPC: H10B12/00 ,  G11C11/402

    Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

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