公开(公告)号：US20160225431A1

公开(公告)日：2016-08-04

申请号：US15098269

申请日：2016-04-13

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  H01L23/48 ,  H01L25/065 ,  G11C11/4096 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20160027498A1

公开(公告)日：2016-01-28

申请号：US14801558

申请日：2015-07-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Scott C. Best ,  Gary B. Bronner

IPC: G11C11/406

CPC classification number: G11C11/40611 ,  G11C2211/4061

Abstract: N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.

Abstract translation: 每个M个刷新命令中的N个被存储器模块上的缓冲器芯片忽略（滤除掉）。 N和M是可编程的。 缓冲器从命令地址信道接收刷新命令（例如，自动刷新命令），但不向模块上的DRAM发出这些命令的一部分。 这减少了刷新操作所消耗的功耗。 缓冲区可以用针对特定行的激活（ACT）和预充电（PRE）命令替换一些自动刷新（REF）命令。 这些行可能具有比模块（或组件）上的大多数其他行更频繁刷新的已知“弱”单元格。 通过忽略一些自动刷新命令，并将一些其他命令指向具有“弱”单元格的特定行，可以减少刷新操作消耗的功率。

公开(公告)号：US09231731B1

公开(公告)日：2016-01-05

申请号：US13857329

申请日：2013-04-05

Applicant: Rambus Inc.

Inventor： Huy M. Nguyen ,  Kambiz Kaviani ,  Reza Navid ,  Jason Chia-Jen Wei ,  Xudong Shi ,  Scott C. Best

IPC: H03K19/094 ,  H04L1/00

CPC classification number: H04L1/0036 ,  H04L25/0276 ,  H04L25/0278

Abstract: The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Abstract translation: 接收差分信号的公共栅极输入放大器的共模输入电压通过基于发射极偏置电流和驱动阻抗的公共栅极放大器的偏置电流和/或源极负载阻抗，以开环方式设置 。 接收差分信号的公共栅极输入放大器的共模输入电压可以使用具有与放大器的节点处的共模输入电压相比的捕获的目标电压的反馈环路以闭环方式设置。 接收差分信号的公共栅极输入放大器的共模输入电压可以通过以参考电流的形式发送参考电流而设置为连续时间闭环方式，电阻是用于产生参考电流的电阻的倍数。

公开(公告)号：US20150357018A1

公开(公告)日：2015-12-10

申请号：US14827771

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract translation: 公开了一种在存储器控制器中的操作方法。 该方法包括接收相对于在第一数据线上传播的第一数据具有第一相位关系的选通信号，以及相对于在第二数据线上传播的第二数据的第二相位关系。 基于第一相位关系产生第一采样信号，并且基于第二相位关系生成第二采样信号。 使用由第一采样信号计时的第一接收机接收第一数据信号。 使用由第二采样信号计时的第二接收机接收第二数据信号。

公开(公告)号：US09159388B2

公开(公告)日：2015-10-13

申请号：US14182389

申请日：2014-02-18

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: H04L7/00 ,  G11C7/22 ,  G06F1/10 ,  G11C7/10 ,  H03L7/07 ,  H03L7/081 ,  H04L7/033 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract translation: 存储器控制器从存储器件接收数据和相位提供信号。 相位提供信号不是时钟信号，而是被存储器控制器用来将本地数据采样信号与输入数据进行相位调整。 存储器控制器用数据采样信号对数据信号进行采样。 存储器控制器可以执行维护操作以更新相位提供和数据采样信号之间的相位关系。

公开(公告)号：US20150228340A1

公开(公告)日：2015-08-13

申请号：US14697182

申请日：2015-04-27

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C14/00

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: A method of controlling a memory device is disclosed. The method includes receiving an address value that indicates a range of addresses within the memory device, each address within the range of addresses corresponding to storage locations within each of two distinct storage dice within the memory device. The address value is stored within a programmable register within the memory device.

Abstract translation: 公开了一种控制存储器件的方法。 该方法包括接收指示存储器设备内的地址范围的地址值，与存储器件内的两个不同存储裸片内的存储位置对应的地址范围内的每个地址。 地址值存储在存储器件内的可编程寄存器内。

公开(公告)号：US20150131388A1

公开(公告)日：2015-05-14

申请号：US14538524

申请日：2014-11-11

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C11/4093 ,  G11C5/04

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20130044552A1

公开(公告)日：2013-02-21

申请号：US13656238

申请日：2012-10-19

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

公开(公告)号：US20250087261A1

公开(公告)日：2025-03-13

申请号：US18904454

申请日：2024-10-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20240095134A1

公开(公告)日：2024-03-21

申请号：US18373219

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

CPC classification number: G06F11/2094 ,  G11C11/4093 ,  G11C29/52 ,  G06F2201/82

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.