公开(公告)号：US20220216133A1

公开(公告)日：2022-07-07

申请号：US17704762

申请日：2022-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC: H01L23/48 ,  H01L23/60 ,  H01L21/768

Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.

公开(公告)号：US20210351139A1

公开(公告)日：2021-11-11

申请号：US17385205

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L23/31 ,  H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L23/522

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

公开(公告)号：US20210265165A1

公开(公告)日：2021-08-26

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20210151550A1

公开(公告)日：2021-05-20

申请号：US17140766

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L49/02 ,  H01L21/311 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US20210020611A1

公开(公告)日：2021-01-21

申请号：US17063251

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Meng-Tse Chen ,  Sheng-Feng Weng ,  Sheng-Hsiang Chiu ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

公开(公告)号：US20200350197A1

公开(公告)日：2020-11-05

申请号：US16934394

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Hui-Min Huang ,  Ai-Tee Ang ,  Yu-Peng Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

公开(公告)号：US10559546B2

公开(公告)日：2020-02-11

申请号：US16233218

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  H01L25/10 ,  H01L21/56 ,  H01L25/00 ,  H01L25/03

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

公开(公告)号：US10535609B2

公开(公告)日：2020-01-14

申请号：US16020030

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Da Tsai ,  Cheng-Ping Lin ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.

公开(公告)号：US10515900B2

公开(公告)日：2019-12-24

申请号：US16222047

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L23/495 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.

公开(公告)号：US20190221544A1

公开(公告)日：2019-07-18

申请号：US16360411

申请日：2019-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Yu-Chih Liu ,  Hui-Min Huang ,  Wei-Hung Lin ,  Jing Ruei Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/563 ,  H01L23/00 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.