PRESSURE SENSOR HAVING A BOSSED DIAPHRAGM
    148.
    发明申请
    PRESSURE SENSOR HAVING A BOSSED DIAPHRAGM 有权
    压力传感器

    公开(公告)号:US20150192486A1

    公开(公告)日:2015-07-09

    申请号:US14543074

    申请日:2014-11-17

    Abstract: A pressure sensor having a diaphragm having a boss with a pattern. The diaphragm having a boss may be regarded as a bossed diaphragm. The bossed diaphragm may have higher sensitivity than a flat plate diaphragm having the same area as the bossed diaphragm. The bossed diaphragm may incorporate a simple cross pattern that can further improve the sensitivity and linearity of a pressure response of the diaphragm at low pressures. Reduction of sharp edges and corners of the boss and its legs around the periphery of the diaphragm may reduce high stress points and thus increase the burst pressure rating of the bossed diaphragm.

    Abstract translation: 一种压力传感器,具有具有带图案的凸台的隔膜。 具有凸台的隔膜可以被认为是凸起的隔膜。 凸起的隔膜可能具有比具有与凸起隔膜相同面积的平板隔膜更高的灵敏度。 凸起的隔膜可以包括简单的交叉图案,其可以进一步提高隔膜在低压下的压力响应的灵敏度和线性。 凸起及其围绕隔膜周边的腿的尖锐边缘和拐角的减小可能会降低高应力点,从而提高凸起隔膜的爆破压力等级。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    150.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号:US20140113412A1

    公开(公告)日:2014-04-24

    申请号:US14135506

    申请日:2013-12-19

    Applicant: XINTEC INC.

    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

    Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法,其包括芯片保护层或附加的蚀刻停止层,以覆盖导电焊盘,以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例,当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时,可以使用芯片保护层,其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层, 形成随后的半导体制造工艺的开口。

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