公开(公告)号：US20140097891A1

公开(公告)日：2014-04-10

申请号：US14101507

申请日：2013-12-10

Applicant: Mosaid Technologies Incorporated

Inventor： Roland Schuetz

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C29/808 ,  H01L23/481 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.

Abstract translation: 通过堆叠多芯片集成电路封装中的硅通孔（TSV）被控制为在其正常任务模式下在封装的现场操作期间根据需要采取不同的连接配置。 可以重新配置TSV连接以以不同于例如该管芯的工厂默认连接的方式连接受影响的管芯。 可以改变与管芯本机电路的输入和/或输出的TSV连接。 芯片可以从互连堆叠中的裸片的接口完全断开，或者原本与此接口断开连接的裸片可能连接到接口。

公开(公告)号：US08677084B2

公开(公告)日：2014-03-18

申请号：US13655582

申请日：2012-10-19

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: G06F13/00

CPC classification number: G06F3/0664 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/068 ,  G06F9/4408 ,  G06F12/0868 ,  G06F2212/217 ,  Y02D10/13 ,  Y02D10/154

Abstract: A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.

Abstract translation: 在具有硬盘驱动器（HDD）和操作系统（O / S）的系统中，提供了一种系统，方法和机器可读介质来配置包括多个NVM模块的非易失性存储器（NVM）。 响应于用户选择NVM的混合驱动模式，根据速度性能对多个NVM模块进行排序。 O / S的引导部分被复制到高排名的NVM模块或多个高排名的NVM模块，并且HDD和高排名的NVM模块被分配为计算机系统的逻辑混合驱动器。 对多个NVM模块中的每一个进行排序可以包括进行速度性能测试。 这种方法可以使用常规硬件提供混合磁盘性能，或提高现有混合驱动器的性能，同时考虑可用的NVM模块的相对性能。

公开(公告)号：US08675425B2

公开(公告)日：2014-03-18

申请号：US13836702

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Roland Schuetz ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

Abstract translation: 存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。 便利减少引脚数接口，将多个选通信号降低到单个选通信号。 此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。 本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

公开(公告)号：US20140036435A1

公开(公告)日：2014-02-06

申请号：US13800897

申请日：2013-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G06F1/20

CPC classification number: G06F1/20 ,  G06F1/203

Abstract: A storage system sized to fit within a standard magnetic hard disk drive (HDD) form factor. The storage system includes a solid state disk (SSD) and a cooling means thermally coupled to the body of the SSD. The components of the SSD occupy a smaller volume of space than magnetic HDD's. In particular, while the SSD has width and length dimensions matching those of the HDD form factor, the SSD has a height dimension that is less than the HDD form factor. Accordingly, the volume of space between the HDD form factor height and the SSD height is beneficially occupied by the cooling means. The storage system can be then be used as a direct replacement for HDD as it can fit within HDD bays configured for the standardized HDD form factor.

Abstract translation: 一种尺寸适合标准磁性硬盘驱动器（HDD）外形尺寸的存储系统。 存储系统包括固态盘（SSD）和热耦合到SSD的主体的冷却装置。 SSD的组件占据比磁性HDD更小的空间。 特别地，虽然SSD的宽度和长度尺寸与HDD外形尺寸相匹配，但SSD的高度尺寸小于HDD外形尺寸。 因此，HDD形状因数高度和SSD高度之间的空间体积被冷却装置有利地占据。 然后可以将存储系统用作HDD的直接替代品，因为它可以适用于为标准化HDD形状因子配置的HDD托架中。

公开(公告)号：US08644108B2

公开(公告)日：2014-02-04

申请号：US13871487

申请日：2013-04-26

Applicant: MOSAID Technologies Incorporated

Inventor： Peter B. Gillingham ,  Graham Allan

IPC: G11C8/00

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract translation: 描述了用于存储器件的时钟模式配置电路。 存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。 可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。 每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从现有存储器件接收源同步时钟信号的串行模式。 根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。 通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

公开(公告)号：US20140022846A1

公开(公告)日：2014-01-23

申请号：US14032816

申请日：2013-09-20

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki KIM

IPC: G11C16/16

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

Abstract translation: 具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。 在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。 当井区的面积减小时，每个井区的电容相应减小。 因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。 或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。 降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

公开(公告)号：US20140016389A1

公开(公告)日：2014-01-16

申请号：US13834009

申请日：2013-03-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Yonghua LIU ,  James KOSOLOWSKI

IPC: G11C11/401

CPC classification number: G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C14/00 ,  G11C29/02 ,  G11C2207/2227 ,  G11C2211/4016

Abstract: A semiconductor device includes a Dynamic Random Access Memory (DRAM) memory array. The DRAM memory array includes a plurality of DRAM memory cells. Each of the DRAM memory cells includes a capacitor. Switching circuitry within the semiconductor device is configured to be switched to a state in which the switching circuitry connects capacitors of at least two of the DRAM memory cells together to provide a bulk capacitance between a first node and a second node.

Abstract translation: 半导体器件包括动态随机存取存储器（DRAM）存储器阵列。 DRAM存储器阵列包括多个DRAM存储单元。 每个DRAM存储单元包括电容器。 半导体器件内的开关电路被配置为切换到其中开关电路将至少两个DRAM存储单元的电容器连接在一起以在第一节点和第二节点之间提供体电容的状态。

公开(公告)号：US20140010019A1

公开(公告)日：2014-01-09

申请号：US14022805

申请日：2013-09-10

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki KIM

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Abstract translation: 一种用于延长闪存设备的使用寿命的方法和系统。 闪存器件是动态配置的，以每单元单位（SBC）存储模式或每单元多位（MBC）模式存储数据。 在MBC存储模式中，单元可以具有多种可能状态之一，其中每个状态由相应的阈值电压范围定义。 在SBC模式中，单元可以具有与彼此不相邻的MBC存储模式的状态对应的阈值电压的状态，以改善单元的可靠性特性。

公开(公告)号：US20140009196A1

公开(公告)日：2014-01-09

申请号：US14023047

申请日：2013-09-10

Applicant: MOSAID Technologies Incorporated

Inventor： Paul W. Demone

IPC: H03L7/06

CPC classification number: H03L7/06 ,  H03K5/00006 ,  H03K5/15046 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/16

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract translation: 一种倍频器电路，包括延迟线，其一端接收用于从多个周期匹配的延迟元件中的相应延迟元件产生时钟抽头输出的参考时钟; 响应于抽头对输出的时钟组合电路，用于从相应的一对输出时钟脉冲的上升沿和下降沿产生，从而输出时钟周期小于输入时钟周期。

公开(公告)号：US20130322173A1

公开(公告)日：2013-12-05

申请号：US13957713

申请日：2013-08-02

Applicant: Mosaid Technologies Incorporated

Inventor： Peter Gillingham ,  Roland Schuetz

IPC: G11C5/02 ,  G11C16/04

CPC classification number: G11C5/025 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4243 ,  G11C16/04

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract translation: 可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。 每个MCD对具有与第二MCD通信的第一MCD。 每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。 响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。 环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。