公开(公告)号：US10008498B2

公开(公告)日：2018-06-26

申请号：US15656385

申请日：2017-07-21

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H03K19/00 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6681 ,  H03K19/0013

Abstract: Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node.

公开(公告)号：US10002616B2

公开(公告)日：2018-06-19

申请号：US15694672

申请日：2017-09-01

Applicant: SOCIONEXT INC.

Inventor： Shuji Miyasaka ,  Kazutaka Abe ,  Zong Xian Liu ,  Yong Hwee Sim ,  Anh Tuan Tran

IPC: H04R5/00 ,  G10L19/008 ,  H04S5/00 ,  G10L19/002 ,  H04S3/00

CPC classification number: G10L19/008 ,  G10L19/002 ,  H04S3/008 ,  H04S5/005 ,  H04S2400/11 ,  H04S2400/15

Abstract: An input signal includes a channel-based audio signal and an object-based audio signal, and an audio encoding device includes an audio scene analysis unit configured to determine an audio scene from the input signal and detect audio scene information; a channel-based encoder that encodes the channel-based audio signal output from the audio scene analysis unit; an object-based encoder that encodes the object-based audio signal output from the audio scene analysis unit; and an audio scene encoding unit configured to encode the audio scene information.

公开(公告)号：US09973186B2

公开(公告)日：2018-05-15

申请号：US14473706

申请日：2014-08-29

Applicant: SOCIONEXT INC.

Inventor： Ian Juso Dedic ,  Saul Darzy ,  Gavin Lambertus Allen

IPC: H03K17/14 ,  H03K17/16 ,  H03K17/30 ,  H03M1/06 ,  H03M1/66 ,  H03M1/68 ,  H03M1/74

CPC classification number: H03K17/145 ,  H03K17/162 ,  H03K17/302 ,  H03M1/0617 ,  H03M1/662 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

公开(公告)号：US09930345B2

公开(公告)日：2018-03-27

申请号：US14871534

申请日：2015-09-30

Applicant: SOCIONEXT INC.

Inventor： Kyousuke Toda

IPC: H04N19/44 ,  H04N19/87 ,  H04N19/85 ,  H04N19/172 ,  H04N19/174 ,  H04N19/107

CPC classification number: H04N19/174 ,  H04N19/107

Abstract: An image encoding apparatus, which is configured to perform image encoding based on a gradual decoder refresh scheme, includes a pre-processor configured to receive a video signal obtained by slicing one screen into a plurality of sub-screens and perform pre-processing, and an image encoder configured to receive output of the pre-processor, perform an encoding process, and generate stream data. The image encoder is configured to acquire information of a first Intra-slice corresponding to a target Intra-slice in a first sequence with respect to the target Intra-slice in a second sequence, in which encoding is performed, after the first sequence; and is configured to estimate an Intra-slice line number and an Inter-slice line number of the second sequence not to exceed a target information amount based on the acquired information of the first Intra-slice.

公开(公告)号：US09880572B2

公开(公告)日：2018-01-30

申请号：US15673197

申请日：2017-08-09

Applicant: SOCIONEXT INC.

Inventor： Yoshinori Okajima ,  Takahiro Ichinomiya ,  Kazuhisa Tanaka ,  Masayuki Taniyama ,  Hidemi Harayama ,  Takeshi Yado

IPC: G05F1/10 ,  G06F1/32

CPC classification number: G05F1/10 ,  G06F1/3296 ,  Y02B70/123 ,  Y02D10/172

Abstract: A semiconductor integrated circuit, supplied with a power source voltage generated by a power supplier and having a level determined in accordance with an analog signal, includes: an output unit outputting, as the analog signal, an output voltage signal indicating the power source voltage; an input unit including an input interface identical in specifications to an output interface of the output unit, and receiving an input signal indicating a voltage and input from an outside of the semiconductor integrated circuit; and a voltage control circuit generating the output voltage signal, based on the input signal and operating voltage information indicating a voltage required for an operation of the semiconductor integrated circuit.

公开(公告)号：US09871033B2

公开(公告)日：2018-01-16

申请号：US15483372

申请日：2017-04-10

Applicant: Socionext Inc.

Inventor： Shiro Usami

IPC: H01L23/52 ,  H01L27/02 ,  H01L29/87 ,  H01L23/528

CPC classification number: H01L27/0292 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0288 ,  H01L29/861 ,  H01L29/87

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

公开(公告)号：US09847777B2

公开(公告)日：2017-12-19

申请号：US15185781

申请日：2016-06-17

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi Ebuchi ,  Seiji Watanabe

IPC: H03K5/08 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/003 ,  H03K3/356

CPC classification number: H03K5/08 ,  H03K3/356 ,  H03K19/00361 ,  H03K19/0175 ,  H03K19/0185

Abstract: Disclosed herein is a signal potential converter which may perform high-speed operation and which may still maintain intended signal amplitude and operate normally even while operating at a low rate or receiving a burst signal. In this signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential at the terminal node, i.e., a signal IN, within the range of a first potential to a second potential. If a potential at the terminal node is higher than a third potential, a voltage holder circuit operates to raise the potential at the terminal node. If the potential at the terminal node is lower than the third potential, the voltage holder circuit operates to lower the potential at the terminal node.

公开(公告)号：US09831271B2

公开(公告)日：2017-11-28

申请号：US15204723

申请日：2016-07-07

Applicant: Socionext Inc.

Inventor： Masaki Tamaru

IPC: H01L27/118 ,  H01L21/768 ,  H01L27/02 ,  H01L23/485 ,  H01L29/10

CPC classification number: H01L27/11807 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/1079 ,  H01L2027/11829 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

公开(公告)号：US09813062B2

公开(公告)日：2017-11-07

申请号：US15080406

申请日：2016-03-24

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi Koike ,  Yasuhiro Agata ,  Yoshinobu Yamagami

IPC: H03K17/12 ,  H03K19/017 ,  H03K19/094 ,  H03K19/0952 ,  H01L21/00 ,  H01L29/00

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

公开(公告)号：US20170264308A1

公开(公告)日：2017-09-14

申请号：US15455988

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： John James DANSON ,  Ian Juso DEDIC ,  Prabhu Ashwin Harold REBELLO

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12

CPC classification number: H03M1/0675 ,  H03M1/0678 ,  H03M1/1009 ,  H03M1/1076 ,  H03M1/1215 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/38

Abstract: There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.