公开(公告)号：US20160365411A1

公开(公告)日：2016-12-15

申请号：US14739543

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Chun-Chen Yeh ,  Xiuyu Cai ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Abstract translation: 实施例涉及制造纳米线场效应晶体管（FET）的一部分的方法。 该方法包括形成牺牲层和纳米线层，去除牺牲层的侧壁部分，并在牺牲层被去除的侧壁部分占据的空间中形成扩散块。 该方法还包括形成源极区域和漏极区域，使得扩散块在牺牲层与源区域和漏极区域中的至少一个之间，以及使用牺牲层去除工艺去除牺牲层，其中扩散 块防止牺牲层去除过程也去除源区和漏区中的至少一个的部分。

公开(公告)号：US09515180B2

公开(公告)日：2016-12-06

申请号：US14588318

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US09466722B2

公开(公告)日：2016-10-11

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160293494A1

公开(公告)日：2016-10-06

申请号：US15180158

申请日：2016-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

公开(公告)号：US20160276275A1

公开(公告)日：2016-09-22

申请号：US15167306

申请日：2016-05-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material.

Abstract translation: MIS接触结构包括半导体材料层，具有形成在其中的接触开口的绝缘材料层，具有基本上垂直取向的部分和基本上水平取向的部分的接触绝缘材料层，接触层的垂直取向部分 绝缘材料接触接触开口的侧壁的部分而不是全部接触半导体层的接触绝缘材料层的水平取向部分。 导电材料位于接触开口内的接触绝缘材料层上，导电材料层具有垂直取向的部分和水平取向的部分，以及定位在接触开口中的导电触点，其接触导电材料层的最上表面， 接触层绝缘材料。

公开(公告)号：US09425292B1

公开(公告)日：2016-08-23

申请号：US15085112

申请日：2016-03-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/00

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括在衬底上形成翅片，在鳍片上形成第一虚拟栅极堆叠和第二虚拟栅极堆叠，形成与鳍片相邻的间隔物，第一伪栅极堆叠和第二虚拟栅极 栅极堆叠，蚀刻以去除所述鳍片的部分并形成由所述间隔物部分地限定的第一空腔，在所述第一腔体中沉积绝缘体材料，在第一虚拟栅极堆叠和所述鳍片的部分上图案化掩模，蚀刻以去除暴露部分 并且在所述鳍的暴露部分上外延生长第一半导体材料。

公开(公告)号：US09425280B2

公开(公告)日：2016-08-23

申请号：US14711196

申请日：2015-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/51

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

Abstract translation: 本文公开的一种方法包括形成邻近牺牲栅极结构的至少一个牺牲侧壁间隔物，所述牺牲栅极结构形成在半导体衬底上方，去除牺牲栅极结构的至少一部分，从而限定由牺牲隔离物横向限定的栅极腔， 在栅极腔中形成替代栅极结构，去除牺牲隔离物，从而限定邻近置换栅极结构的间隔空腔，并在间隔空腔中形成低k隔离物。 本文公开的新型器件包括位于半导体衬底上方的栅极结构，其中栅绝缘层具有相对于衬底的上表面基本上垂直取向的两个直立部分。 该装置还包括邻近栅极绝缘层的垂直取向的竖立部分的低k侧壁间隔件。

公开(公告)号：US09412740B2

公开(公告)日：2016-08-09

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US09391200B2

公开(公告)日：2016-07-12

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。

公开(公告)号：US09349840B2

公开(公告)日：2016-05-24

申请号：US14883049

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 一种说明性的方法包括在包括半导体衬底，第一外延半导体材料和第二外延半导体材料的结构之上形成FinFET器件，其包括形成包括半导体衬底，第一外延材料和第二外延材料的部分的初始鳍结构 使一层绝缘材料凹陷，使得初始翅片结构的第二外延材料部分的一部分（但不是全部）暴露以便限定最终的翅片结构，在最后的翅片结构的上方和周围形成栅极结构， 去除初始翅片结构的第一外延材料，从而在最终翅片结构下限定底鳍腔，并用应力材料基本上填充底鳍腔。