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    Apparatuses and methods for sensing using an integration component
    161.
    发明授权
    Apparatuses and methods for sensing using an integration component 有权
    使用集成组件进行感测的装置和方法

    公开(公告)号：US09330756B2

    公开(公告)日：2016-05-03

    申请号：US14458813

    申请日：2014-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/00 ,  G11C11/1677 ,  G11C13/0064 ,  G11C2013/0066

    Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided.

    Abstract translation: 本公开包括用于感测电阻变量存储单元的装置和方法。 许多实施例包括向阵列中的存储器单元提供编程信号的电路，与将存储器单元编程为特定数据状态相关联的编程信号; 并且通过积分分量确定响应于所提供的编程信号，存储器单元的数据状态是否变为不同的数据状态。

    STATE DETERMINATION IN RESISTANCE VARIABLE MEMORY
    163.
    发明申请
    STATE DETERMINATION IN RESISTANCE VARIABLE MEMORY 有权
    电阻可变存储器中的状态确定

    公开(公告)号：US20150187416A1

    公开(公告)日：2015-07-02

    申请号：US14656908

    申请日：2015-03-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ferdinando Bedeschi

    IPC: G11C13/00 ,  G11C7/06 ,  G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C11/161 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/0002 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0047 ,  G11C2013/0057

    Abstract: An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell to switch from a first state to a second state. Responses from the memory cell are sensed at three or more sample points. Differences between the responses are determined. For example, with three sample points, a first delta is determined between the first two responses and a second delta is determined between the last two responses. A difference of deltas is determined as a difference between the first and second delta, or vice versa. It is determined that the memory cell changes from the first to the second state if the difference of deltas is above a threshold. It is determined that the memory cell remains in the second state if the difference of deltas is below the threshold.

    Abstract translation: 将评估信号施加到电阻变量存储单元阵列中的存储单元。 评估信号被配置为使存储单元从第一状态切换到第二状态。 在三个或更多个采样点处感测来自存储器单元的响应。 确定响应之间的差异。 例如，对于三个采样点，在前两个响应之间确定第一增量，并且在最后两个响应之间确定第二增量。 三角洲差异被确定为第一和第二增量之间的差异，反之亦然。 如果三角波的差异高于阈值，则确定存储器单元从第一状态变为第二状态。 如果三角形的差值低于阈值，则确定存储器单元保持在第二状态。

    APPARATUS AND METHOD FOR READING A PHASE-CHANGE MEMORY CELL
    164.
    发明申请
    APPARATUS AND METHOD FOR READING A PHASE-CHANGE MEMORY CELL 有权
    用于读取相变存储器单元的装置和方法

    公开(公告)号：US20150155034A1

    公开(公告)日：2015-06-04

    申请号：US14615788

    申请日：2015-02-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ferdinando Bedeschi

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: An Apparatus and a method for reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled with the current ramp circuit. A Veb emulation circuit is coupled with the current forcing module by a voltage adder, the voltage adder to sum an output from the Veb emulation circuit and a high impedance voltage source. A method includes forcing a current ramp into both a bitline and a dummy bitline, the dummy bitline having a voltage. The method also includes tripping a comparator when the current ramp provides a storage voltage with a predefined value, the storage voltage associated with the phase-change memory cell, and the predefined value independent from a resistance value of the phase-change memory cell and added in series to the voltage of the dummy bitline.

    Abstract translation: 描述了一种用于读取相变存储单元的装置和方法。 电路包括电流斜坡电路。 电流强制模块与电流斜坡电路耦合。 Veb仿真电路通过电压加法器与电流强制模块耦合，电压加法器将来自Veb仿真电路的输出和高阻抗电压源相加。 一种方法包括将电流斜坡强制施加到位线和伪位线中，虚拟位线具有电压。 该方法还包括当电流斜坡提供具有预定义值的存储电压时，跳闸比较器，与相变存储器单元相关联的存储电压以及独立于相变存储器单元的电阻值的预定值并且被添加 与虚拟位线的电压串联。

    Performing sense operations in memory
    169.
    发明授权
    Performing sense operations in memory 有权

    公开(公告)号：US12288592B2

    公开(公告)日：2025-04-29

    申请号：US17873991

    申请日：2022-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

    IPC: G11C29/50

    Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

    Shared decoder architecture for three-dimensional memory arrays
    170.
    发明授权
    Shared decoder architecture for three-dimensional memory arrays 有权

    公开(公告)号：US12260907B2

    公开(公告)日：2025-03-25

    申请号：US18622033

    申请日：2024-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

    IPC: G11C13/04 ,  G11C13/00

    Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.

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