公开(公告)号：US12086441B2

公开(公告)日：2024-09-10

申请号：US17461105

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Steven C. Woo ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F1/08

CPC classification number: G06F3/064 ,  G06F1/08 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0688

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.

公开(公告)号：US20240242741A1

公开(公告)日：2024-07-18

申请号：US18420688

申请日：2024-01-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L23/481 ,  H01L25/0657 ,  H10B12/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US20240153548A1

公开(公告)日：2024-05-09

申请号：US18503022

申请日：2023-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/2245

Abstract: Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.

公开(公告)号：US20240086112A1

公开(公告)日：2024-03-14

申请号：US18470232

申请日：2023-09-19

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673

Abstract: A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.

公开(公告)号：US11822822B2

公开(公告)日：2023-11-21

申请号：US17824665

申请日：2022-05-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/109 ,  G11C7/1087 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US11790973B2

公开(公告)日：2023-10-17

申请号：US17376032

申请日：2021-07-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/34 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091

CPC classification number: G11C11/403 ,  G06F12/06 ,  G11C5/025 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/18 ,  G11C8/08 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40618 ,  G11C11/4091

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US20220238141A1

公开(公告)日：2022-07-28

申请号：US17568649

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065 ,  G11C5/02

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US11341086B2

公开(公告)日：2022-05-24

申请号：US17093227

申请日：2020-11-09

Applicant: Rambus Inc.

Inventor： Amogh Agrawal ,  Thomas Vogelsang ,  Steven C. Woo

IPC: G06F15/80

Abstract: An array of processing elements are arranged in a three-dimensional array. Each of the processing elements includes or is coupled to a dedicated memory. The processing elements of the array are intercoupled to their nearest neighbor processing elements. A processing element on a first die may be intercoupled to a first processing element on a second die that is located directly above the processing element, a second processing element on a third die that is located directly below the processing element, and the four adjacent processing elements on the first die. This intercoupling allows data to flow from processing element to processing element in the three directions. These dataflows are reconfigurable so that they may be optimized for the task. The data flows of the array may be configured into one or more loops that periodically recycle data in order to accomplish different parts of a calculation.

公开(公告)号：US20210233599A1

公开(公告)日：2021-07-29

申请号：US17226216

申请日：2021-04-09

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  William Ng ,  Frederick A. Ware

IPC: G11C29/02 ,  H01L25/065 ,  H01L21/66 ,  G01R31/28 ,  G11C8/10 ,  G11C29/04 ,  G11C5/02 ,  G11C5/06

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

公开(公告)号：US11069392B2

公开(公告)日：2021-07-20

申请号：US17099413

申请日：2020-11-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/24 ,  G11C11/403 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4097 ,  G11C11/4091

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.