公开(公告)号：US20230386826A1

公开(公告)日：2023-11-30

申请号：US18358508

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/0217 ,  H01L21/76224 ,  H01L21/0337 ,  H01L21/02208 ,  H01L21/3086 ,  H01L21/0228 ,  H01L29/66795 ,  H01L21/3081 ,  H01L29/66545 ,  H01L21/823431 ,  H01L29/785

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US11830727B2

公开(公告)日：2023-11-28

申请号：US17809917

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0217 ,  H01L21/0228 ,  H01L21/02208 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US11822237B2

公开(公告)日：2023-11-21

申请号：US17071004

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui Weng ,  Chen-Yu Liu ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Jia-Lin Wei ,  Yen-Yu Chen ,  Jr-Hung Li ,  Yahru Cheng ,  Chi-Ming Yang ,  Tze-Liang Lee ,  Ching-Yu Chang

IPC: G03F7/004 ,  H01L21/033 ,  G03F7/00

CPC classification number: G03F7/004 ,  G03F7/0035 ,  H01L21/0332

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

公开(公告)号：US20230369048A1

公开(公告)日：2023-11-16

申请号：US18227231

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin WEI ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  H01L21/308 ,  G03F7/00 ,  G03F1/22

CPC classification number: H01L21/0332 ,  H01L21/3081 ,  G03F7/70033 ,  G03F1/22 ,  H01L21/0334

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US20230282750A1

公开(公告)日：2023-09-07

申请号：US17841493

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang ,  Hao-Yu Chang ,  Pei-Yu Chou

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.

公开(公告)号：US20230274977A1

公开(公告)日：2023-08-31

申请号：US17681207

申请日：2022-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Tze-Liang Lee

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76834 ,  H01L21/76802 ,  H01L21/76843

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over an integrated circuit device; forming a first conductive feature in the first dielectric layer; selectively depositing a polymer layer over the first conductive feature; selectively depositing an etch stop layer over the first dielectric layer adjacent the polymer layer; removing the polymer layer to form a first opening; and forming a second conductive feature in the first opening and electrically coupled to the first conductive feature.

公开(公告)号：US20230260829A1

公开(公告)日：2023-08-17

申请号：US18308937

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/76879 ,  H01L21/31144 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/02211 ,  H01L21/0337

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US20230187511A1

公开(公告)日：2023-06-15

申请号：US18166379

申请日：2023-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/41733 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/66742 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L29/785

Abstract: A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. An etch stop layer is deposited over the dielectric cap. An interlayer dielectric (ILD) layer is deposited over the etch stop layer. The ILD layer is in contact with a sidewall of the etch stop layer. A gate via in the ILD layer is formed to pass through the etch stop layer and the dielectric cap to the gate structure.

公开(公告)号：US20230178446A1

公开(公告)日：2023-06-08

申请号：US17657184

申请日：2022-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Jen Sung ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3185 ,  H01L24/73 ,  H01L24/08 ,  H01L23/5386 ,  H01L21/56 ,  H01L23/3192 ,  H01L23/291 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L2225/1041 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L25/105

Abstract: A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

公开(公告)号：US20230154992A1

公开(公告)日：2023-05-18

申请号：US17651671

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Liang Lee ,  Po-Hsien Cheng ,  Po-Cheng Shih

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/41775 ,  H01L29/66795 ,  H01L29/6656 ,  H01L21/823431 ,  H01L29/41791

Abstract: A structure includes a gate stack over a semiconductor region, a source/drain region on a side of the gate stack, a contact etch stop layer over a part of the source/drain region, an inter-layer dielectric over the contact etch stop layer, a silicide region over the source/drain region, a source/drain contact plug over and contacting the silicide region, and an isolation layer encircling the source/drain contact plug. In a top view of the source/drain contact plug, the source/drain contact plug is elongated, and the isolation layer includes an end portion at an end of the source/drain contact plug, and a middle portion between opposing ends of the source/drain contact plug. An end-portion thickness of the end portion is greater than a middle-portion thickness of the middle portion.