公开(公告)号：US20140170817A1

公开(公告)日：2014-06-19

申请号：US14184999

申请日：2014-02-20

Applicant: Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Sil-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Sil-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract translation: 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Sil-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Sil-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突出部。

公开(公告)号：US08722478B2

公开(公告)日：2014-05-13

申请号：US12885071

申请日：2010-09-17

Applicant: Been-Yin Jin ,  Brian S Doyle ,  Jack T Kavalieros ,  Robert S Chau

Inventor： Been-Yin Jin ,  Brian S Doyle ,  Jack T Kavalieros ,  Robert S Chau

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract translation: 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

公开(公告)号：US08716751B2

公开(公告)日：2014-05-06

申请号：US13631417

申请日：2012-09-28

Applicant: Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L21/02

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US08592803B2

公开(公告)日：2013-11-26

申请号：US13442098

申请日：2012-04-09

Applicant: Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/06 ,  H01L29/778

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US08558279B2

公开(公告)日：2013-10-15

申请号：US12924232

申请日：2010-09-23

Applicant: Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract translation: 根据该方法制造的方法和装置。 该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配 。 提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

公开(公告)号：US08518768B2

公开(公告)日：2013-08-27

申请号：US13450359

申请日：2012-04-18

Applicant: Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Majumdar Amian ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Majumdar Amian ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L21/70 ,  H01L21/8238

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract translation: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

公开(公告)号：US08487348B2

公开(公告)日：2013-07-16

申请号：US13588416

申请日：2012-08-17

Applicant: Stephen M. Cea ,  Martin D. Giles ,  Kelin Kuhn ,  Jack T. Kavalieros ,  Markus Kuhn

Inventor： Stephen M. Cea ,  Martin D. Giles ,  Kelin Kuhn ,  Jack T. Kavalieros ,  Markus Kuhn

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7842

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.

Abstract translation: 本公开涉及制造微电子器件的领域。 在至少一个实施例中，本公开涉及在保持半导体本体中的应变的同时在非平面晶体管的应变半导体本体中形成隔离结构。

公开(公告)号：US08421059B2

公开(公告)日：2013-04-16

申请号：US12898211

申请日：2010-10-05

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

IPC: H01L49/00 ,  H01L21/70

CPC classification number: H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

公开(公告)号：US08368052B2

公开(公告)日：2013-02-05

申请号：US12646621

申请日：2009-12-23

Applicant: Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/66

CPC classification number: H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract translation: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。

公开(公告)号：US08362566B2

公开(公告)日：2013-01-29

申请号：US12144469

申请日：2008-06-23

Applicant: Titash Rakshit ,  Martin Giles ,  Ravi Pillarisetty ,  Jack T. Kavalieros

Inventor： Titash Rakshit ,  Martin Giles ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L21/70

CPC classification number: H01L29/7845 ,  H01L21/8234 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.