公开(公告)号：US10109724B2

公开(公告)日：2018-10-23

申请号：US15614471

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li ,  Miguel Miranda Corbalan

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.

公开(公告)号：US10102895B1

公开(公告)日：2018-10-16

申请号：US15686424

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C11/16 ,  G11B5/39 ,  G11C11/15 ,  H01L43/08 ,  H01L27/105 ,  G11C11/412

Abstract: Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration are disclosed. In one aspect, an MRAM bit cell includes a magnetic tunnel junction (MTJ) device and an access transistor used to control reading and writing of the MRAM bit cell. To reduce or avoid source degeneration caused by a voltage at a source region of the access transistor in response to a write operation, a back gate bias voltage is applied to a back gate electrode of the access transistor, the back gate bias voltage controlled to be greater than or equal to a back gate voltage associated with the access transistor having a nominal threshold voltage corresponding to operation without source degeneration plus a voltage corresponding to the source region of the access transistor.

公开(公告)号：US20180284200A1

公开(公告)日：2018-10-04

申请号：US15474339

申请日：2017-03-30

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Wah Nam Hsu ,  Xia Li ,  Seung Hyuk Kang ,  Nicholas Ka Ming Stevens-Yu

IPC: G01R33/09 ,  H01L43/08 ,  H01L27/22 ,  G01R33/12

Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.

公开(公告)号：US20180240890A1

公开(公告)日：2018-08-23

申请号：US15962023

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/765 ,  H01L21/762 ,  H01L27/02

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

公开(公告)号：US10043826B1

公开(公告)日：2018-08-07

申请号：US15660288

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L29/423 ,  H01L27/12 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/683 ,  H01L21/02 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a first non-insulative region disposed above the substrate, and a second non-insulative region disposed above the first non-insulative region, wherein the first and second non-insulative regions have the same doping type and different doping concentrations. In certain aspects, the semiconductor device also includes a first dielectric layer, a channel region, the first dielectric layer being disposed adjacent to a first side of the channel region, a second dielectric layer disposed adjacent to a second side of the channel region, and a third non-insulative region disposed above the second dielectric layer. In certain aspects, the semiconductor device also includes a fourth non-insulative region disposed adjacent to a third side of the channel region, and a fifth non-insulative region disposed adjacent to a fourth side of the channel region.

公开(公告)号：US20180190338A1

公开(公告)日：2018-07-05

申请号：US15829004

申请日：2017-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Seung Hyuk Kang

IPC: G11C11/22 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/49 ,  H01L29/47 ,  H01L29/51 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: G11C11/2275 ,  G11C11/22 ,  G11C11/223 ,  G11C13/003 ,  H01L21/02148 ,  H01L21/02197 ,  H01L21/02532 ,  H01L21/28291 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1159 ,  H01L29/16 ,  H01L29/47 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/66765 ,  H01L29/6684 ,  H01L29/7839 ,  H01L29/78391 ,  H01L29/78669 ,  H01L29/78678

Abstract: Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.

公开(公告)号：US10008537B2

公开(公告)日：2018-06-26

申请号：US14744984

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Yu Lu

IPC: G11C11/15 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L27/226 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A complementary bit cell includes a first magnetic tunnel junction (MTJ) device having a free layer coupled to a first access transistor and having a pinned layer coupled to a bit line. The complementary bit cell also includes a second MTJ device having a free layer coupled to the same bit line and having a pinned layer coupled to a second access transistor.

公开(公告)号：US09966149B2

公开(公告)日：2018-05-08

申请号：US15450055

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C11/00 ,  G11C17/02 ,  G11C11/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

公开(公告)号：US09876123B2

公开(公告)日：2018-01-23

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  G11C17/18 ,  H01L27/112 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

公开(公告)号：US09842802B2

公开(公告)日：2017-12-12

申请号：US14227415

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

IPC: H01L21/82 ,  H01L27/112 ,  H01L21/8239 ,  H01L23/525 ,  G11C17/16 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5252 ,  G11C17/16 ,  H01L23/5228 ,  H01L27/11206 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.