公开(公告)号：US20170148730A1

公开(公告)日：2017-05-25

申请号：US15423923

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US09614057B2

公开(公告)日：2017-04-04

申请号：US14585572

申请日：2014-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions.

公开(公告)号：US09601386B1

公开(公告)日：2017-03-21

申请号：US14851838

申请日：2015-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/823878 ,  H01L27/1211

Abstract: A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices. and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate.

公开(公告)号：US09595473B2

公开(公告)日：2017-03-14

申请号：US14727132

申请日：2015-06-01

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

Abstract translation: 制造自对准通孔结构的方法包括在下金属布线层上的ILD层上形成三层掩模，所述三层掩模包括第一绝缘层和第二绝缘层以及绝缘层之间的金属层; 通过所述第一绝缘层和金属层限定沟槽图案，所述沟槽图案具有第一宽度; 在所述沟槽图案上的光刻掩模中限定第一通孔图案，所述第一通孔图案具有大于所述第一宽度的第二宽度; 在沟槽图案的暴露的侧壁上生长金属覆盖层，以将第一宽度减小到限定第二通孔图案的第三宽度; 将沟槽图案转移到ILD层中以形成沟槽; 并且将第二通孔图案通过ILD层转移到金属布线层中以形成通孔。

公开(公告)号：US09583626B2

公开(公告)日：2017-02-28

申请号：US14699491

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/324 ,  H01L21/322

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/322 ,  H01L21/3221 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

Abstract translation: 在硅片的侧壁表面上形成硅锗合金。 采用氧化工艺或热退火将硅片的一部分转换成硅锗合金翅片。 在一些实施例中，硅锗合金翅片具有宽的上部和较窄的下部。 在这样的实施例中，宽的上部具有比较窄的下部更大的锗含量。 在其他实施例中，硅锗合金翅片具有窄的上部和较宽的下部。 在本实施例中，硅锗合金翅片的较窄上部具有比硅锗合金翅片的较宽下部更大的锗含量。

公开(公告)号：US20170047445A1

公开(公告)日：2017-02-16

申请号：US14823344

申请日：2015-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/165 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

Abstract translation: 用于形成杂化互补金属氧化物半导体（CMOS）器件的方法包括将绝缘体上半导体（SOI）衬底的半导体层与SOI的基底衬底取向，通过蚀刻将基底衬底暴露在N阱区中 通过掩模层，电介质层，半导体层和掩埋电介质形成沟槽并在沟槽的侧壁上形成间隔物。 基底衬底从沟槽的底部外延生长以形成延伸区域。 翅片材料从沟槽内的延伸区域外延生长。 掩模层和电介质层在沟槽上恢复。 P型场效应晶体管（PFET）鳍片被蚀刻在基底衬底上，并且在半导体层中蚀刻N型场效应晶体管（NFET）鳍片。

公开(公告)号：US20170040417A1

公开(公告)日：2017-02-09

申请号：US14819244

申请日：2015-08-05

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Hong He ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/1054 ,  H01L21/76254 ,  H01L29/7842

Abstract: A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer. The silicon device layer has a tensily-strained region overlying the silicon-germanium feature. Regions of the silicon device layer not overlying the silicon-germanium feature are less strained than the tensily-strained region. The tensily-strained region of the silicon device layer may be further processed into channel features in n-type field effect transistors with improved charge carrier mobilities and device drive currents.

Abstract translation: 提供了一种用于形成集成电路的方法。 在衬底中形成沟槽。 随后，在沟槽中形成硅 - 锗特征，并且在衬底上和硅 - 锗特征上形成蚀刻停止层。 最后，在蚀刻停止层上形成硅器件层。 硅器件层具有覆盖硅 - 锗特征的紧张应变区域。 没有覆盖硅 - 锗特征的硅器件层的区域比紧张应变区域的应变小。 硅器件层的紧张应变区域可以进一步处理成具有改进的电荷载流子迁移率和器件驱动电流的n型场效应晶体管的沟道特征。

公开(公告)号：US09536986B2

公开(公告)日：2017-01-03

申请号：US14743504

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions.

Abstract translation: 实施例涉及一种对FinFET的鳍进行富集和电绝缘的方法。 该方法包括形成至少一个翅片。 所述方法还包括在第一组条件下形成所述至少一个翅片的富集的上部部分。 所述方法还包括在第二组条件下形成与所述至少一个翅片的下部分的电隔离区域，其中在所述第一组条件下的形成与所述第二组条件下的成形间隔开。 该方法还包括与第二组条件分开地控制第一组条件。

公开(公告)号：US09515089B1

公开(公告)日：2016-12-06

申请号：US14712072

申请日：2015-05-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76202 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656

Abstract: Fabricating a semiconductor device includes providing a substrate, wherein the substrate is comprised of a base layer, a doped silicon layer on top of the base layer, and an undoped silicon layer on top of the doped silicon layer; forming a hard mask layer on top of the substrate; forming at least one mandrel on top of the hard mask layer; forming a spacer layer on top of exposed portions of the hard mask layer and the at least one mandrel; etching portions of the spacer layer; removing the at least one mandrel; etching regions of the hard mask layer and the undoped silicon layer not protected by remaining portions of the spacer layer to form at least one fin; and removing the remaining portions of the spacer layer.

Abstract translation: 制造半导体器件包括提供衬底，其中衬底由基底层，基底层顶部的掺杂硅层和掺杂硅层顶部的未掺杂硅层构成; 在所述基板的顶部上形成硬掩模层; 在所述硬掩模层的顶部上形成至少一个心轴; 在所述硬掩模层和所述至少一个心轴的暴露部分的顶部上形成间隔层; 蚀刻间隔层的部分; 移除所述至少一个心轴; 蚀刻所述硬掩模层和未掺杂的硅层的区域，而不被所述间隔层的剩余部分保护以形成至少一个鳍; 并去除间隔层的剩余部分。

公开(公告)号：US09508741B2

公开(公告)日：2016-11-29

申请号：US14618397

申请日：2015-02-10

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L23/48 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/027 ,  H01L27/092

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849

Abstract: A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.

Abstract translation: 描述了在包括p型场效应晶体管器件（pFET）和n型场效应晶体管（nFET）器件和CMOS器件的互补金属氧化物半导体（CMOS）器件中形成鳍的方法。 该方法包括在pFET区域和nFET区域中形成应变绝缘体上硅（silicon-on-insulator，SSOI）层，仅在pFET区域中蚀刻应变硅层，绝缘体和一部分本体衬底以暴露体 衬底，仅在pFET区域中从体衬底外延生长硅（Si），并且在仅在pFET区域中在Si上外延生长另外的半导体材料。 该方法还包括从附加半导体材料形成散热片和在pFET区域中在体衬底上生长的Si的一部分，以及从nFET区域中的应变硅层和绝缘体形成翅片。