公开(公告)号：US20180308933A1

公开(公告)日：2018-10-25

申请号：US16022737

申请日：2018-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/02634 ,  H01L21/3085 ,  H01L21/76278 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.

公开(公告)号：US20180301336A1

公开(公告)日：2018-10-18

申请号：US15489842

申请日：2017-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/76224 ,  H01L29/66795

Abstract: A method of pattern transfer is provided, comprising: providing a target layer; forming a first pattern above the target layer; forming a second pattern (such as spacer loops) above the target layer and above the first pattern, wherein one closed end of the second pattern partially overlaps with the first pattern; and transferring the second pattern to the target layer, wherein the first pattern stops transferring pattern of the closed end of the second pattern to the target layer.

公开(公告)号：US20180239235A1

公开(公告)日：2018-08-23

申请号：US15481479

申请日：2017-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/24 ,  G03F1/22

Abstract: An extreme ultraviolet (EUV) mask includes: a substrate having a first region and a second region; a reflective layer on the substrate; an absorbing layer on the reflective layer; and a first recess in the absorbing layer and in part of the reflective layer on the first region. Preferably, a bottom surface of the first recess exposes a top surface of the reflective layer.

公开(公告)号：US20180233419A1

公开(公告)日：2018-08-16

申请号：US15495942

申请日：2017-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/66 ,  H01L23/544

CPC classification number: H01L22/12 ,  G03F7/70633 ,  G03F7/70683 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

公开(公告)号：US10043807B1

公开(公告)日：2018-08-07

申请号：US15641236

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Cheng Tung ,  Chun-Tsen Lu ,  En-Chiuan Liou ,  Kuan-Hung Chen

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.

公开(公告)号：US20180053761A1

公开(公告)日：2018-02-22

申请号：US15242591

申请日：2016-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/308 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

公开(公告)号：US09899267B1

公开(公告)日：2018-02-20

申请号：US15390527

申请日：2016-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L21/70 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure.

公开(公告)号：US20180040693A1

公开(公告)日：2018-02-08

申请号：US15786611

申请日：2017-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

公开(公告)号：US20180033891A1

公开(公告)日：2018-02-01

申请号：US15253908

申请日：2016-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： XIAODONG PU ,  Shao-Hui Wu ,  HAI BIAO YAO ,  Qinggang Xing ,  Chien-Ming Lai ,  Jun Zhu ,  Yu-Cheng Tung ,  ZHIBIAO ZHOU

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78648

Abstract: An oxide semiconductor device includes an oxide semiconductor transistor and a protection wall. The protection wall extends in a vertical direction and surrounds the oxide semiconductor transistor. The oxide semiconductor transistor includes a first oxide semiconductor layer, and a bottom surface of the protection wall is lower than the first oxide semiconductor layer in the vertical direction. In the oxide semiconductor device of the present invention, the protection wall is used to surround the oxide semiconductor transistor for improving the ability of blocking environment substances from entering the oxide semiconductor transistor. The electrical stability and product reliability of the oxide semiconductor device are enhanced accordingly.

公开(公告)号：US09875937B2

公开(公告)日：2018-01-23

申请号：US15356671

申请日：2016-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/322 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L21/324 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.