公开(公告)号：US08269283B2

公开(公告)日：2012-09-18

申请号：US12653971

申请日：2009-12-21

Applicant: Stephen M. Cea ,  Martin D. Giles ,  Kelin Kuhn ,  Jack T. Kavalieros ,  Markus Kuhn

Inventor： Stephen M. Cea ,  Martin D. Giles ,  Kelin Kuhn ,  Jack T. Kavalieros ,  Markus Kuhn

IPC: H01L21/70

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7842

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.

Abstract translation: 本公开涉及制造微电子器件的领域。 在至少一个实施例中，本公开涉及在保持半导体本体中的应变的同时在非平面晶体管的应变半导体本体中形成隔离结构。

公开(公告)号：US20120211726A1

公开(公告)日：2012-08-23

申请号：US13461962

申请日：2012-05-02

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US20120074464A1

公开(公告)日：2012-03-29

申请号：US12924232

申请日：2010-09-23

Applicant: Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract translation: 根据该方法制造的方法和装置。 该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配 。 提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

公开(公告)号：US08129749B2

公开(公告)日：2012-03-06

申请号：US12058063

申请日：2008-03-28

Applicant: Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Jack T. Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Jack T. Kavalieros

IPC: H01L29/66

CPC classification number: H01L29/7785 ,  H01L29/205 ,  H01L29/7783

Abstract: Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier layer wherein the first quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof, a second barrier layer coupled to the first quantum well channel, and a second quantum well channel coupled to the barrier layer wherein the second quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof.

Abstract translation: 通常描述晶体管的双量子阱结构。 在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，与第一势垒层耦合的第一量子阱沟道，其中第一量子 阱沟道包括III-V族半导体材料或II-VI族半导体材料或其组合，耦合到第一量子阱沟道的第二阻挡层和耦合到阻挡层的第二量子阱沟道，其中第二量子 阱沟道包括III-V族半导体材料或II-VI族半导体材料或其组合。

公开(公告)号：US20110291192A1

公开(公告)日：2011-12-01

申请号：US13205002

申请日：2011-08-08

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/06 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Abstract translation: 通常描述用于增加多栅极晶体管器件中的体掺杂物均匀性的技术和结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的多栅极鳍片，多栅极鳍片，包括源极区域，漏极区域和栅极区域，其中栅极区域设置在源极 区域和漏极区域，在从多栅极鳍去除牺牲栅极结构之后并且在形成后续栅极结构之后，栅极区域被体掺杂，与多层栅极的源极区域和漏极区域耦合的介电材料 并且随后的栅极结构耦合到多栅极鳍的栅极区域。

公开(公告)号：US07999298B2

公开(公告)日：2011-08-16

申请号：US12319101

申请日：2008-12-30

Applicant: Jack T. Kavalieros ,  Niloy Mukherjee ,  Gilbert Dewey ,  Dinesh Somasekhar ,  Brian S. Doyle

Inventor： Jack T. Kavalieros ,  Niloy Mukherjee ,  Gilbert Dewey ,  Dinesh Somasekhar ,  Brian S. Doyle

IPC: H01L27/108

CPC classification number: H01L29/66181 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10876 ,  H01L28/90 ,  H01L29/66666 ,  H01L29/7827

Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

Abstract translation: 嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。 电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。 第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

公开(公告)号：US20110147711A1

公开(公告)日：2011-06-23

申请号：US12646477

申请日：2009-12-23

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC: H01L29/06 ,  H01L21/338

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract translation: 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20110121266A1

公开(公告)日：2011-05-26

申请号：US13017862

申请日：2011-01-31

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/06 ,  H01L21/20

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US07928426B2

公开(公告)日：2011-04-19

申请号：US11728891

申请日：2007-03-27

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/06

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US20110062520A1

公开(公告)日：2011-03-17

申请号：US12949696

申请日：2010-11-18

Applicant: Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。