公开(公告)号：US09564471B2

公开(公告)日：2017-02-07

申请号：US15095208

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L27/08 ,  H01L27/24 ,  H01L27/10 ,  H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H01L27/115 ,  H01L45/00

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US09543433B2

公开(公告)日：2017-01-10

申请号：US14217844

申请日：2014-03-18

Applicant: Micron Technology, Inc.

Inventor： Venkatesan Anathan ,  Sanh D. Tang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66621

Abstract: A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.

Abstract translation: 具有由具有不同功函数的两个或多个栅极材料形成的栅电极的凹陷存取装置可以减小来自凹陷存取装置的栅极引起的漏极漏电流损耗。 栅电极可以包括具有设置在凹陷入口装置的底部中的高功函的第一栅极材料和具有设置在第一栅极材料上的下功函数的第二栅极材料以及凹陷入口装置的上部 。

公开(公告)号：US09391092B2

公开(公告)日：2016-07-12

申请号：US14929853

申请日：2015-11-02

Applicant: Micron Technology, Inc.

Inventor： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/36 ,  H01L21/84 ,  H01L29/78 ,  H01L27/108 ,  H01L45/00 ,  H01L27/24 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

Abstract translation: 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

公开(公告)号：US20160155936A1

公开(公告)日：2016-06-02

申请号：US15003715

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

公开(公告)号：US09356096B2

公开(公告)日：2016-05-31

申请号：US14803662

申请日：2015-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Song Guo ,  Yushi Hu ,  Roy Meade ,  Sanh D. Tang ,  Michael P. Violette ,  David H. Wells

IPC: H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/32

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/04 ,  H01L29/32

Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.

公开(公告)号：US20160118392A1

公开(公告)日：2016-04-28

申请号：US14987370

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/04 ,  H01L29/788 ,  H01L29/167

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

Abstract translation: 描述形成多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，在半导体材料层和电介质层中形成开口。 通过开口暴露的半导体材料层的一部分被处理，使得该部分与该层中剩余的半导体材料不同地掺杂。 至少基本上所有剩余的层的半导体材料被去除，留下半导体材料层的不同掺杂部分作为电荷存储结构。 在电荷存储结构的第一表面上形成隧道电介质，并且在电荷存储结构的第二表面上形成隔间电介质。 还描述了另外的实施例。

公开(公告)号：US20160056175A1

公开(公告)日：2016-02-25

申请号：US14929853

申请日：2015-11-02

Applicant: Micron Technology, Inc.

Inventor： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

IPC: H01L27/12 ,  H01L23/528 ,  H01L27/24 ,  H01L29/36 ,  H01L27/108 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

Abstract translation: 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

公开(公告)号：US20150349248A1

公开(公告)日：2015-12-03

申请号：US14812284

申请日：2015-07-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

Abstract: A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

Abstract translation: 形成相变材料存储单元的方法包括形成多个存储结构区域，其中存储结构区域包括底电极材料和牺牲材料，在存储结构区域的数量之间形成多个绝缘体区域，形成 多个绝缘体区域之间的开口数，并且通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成绝缘体区域的轮廓表面，在绝缘体区域的数量上形成多个电介质间隔物，形成绝缘体区域 在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分介电间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。

公开(公告)号：US20150179649A1

公开(公告)日：2015-06-25

申请号：US14642866

申请日：2015-03-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L27/102 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3205 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/1027 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/401 ,  H01L29/42308 ,  H01L29/66363 ,  H01L29/749

Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract translation: 提供了包括多个基于晶闸管的存储单元的半导体器件，每个存储单元的单元尺寸为4F2，以及形成该晶体管的存储单元的形成方法。 基于晶闸管的存储单元各自包括具有交替掺杂剂类型的垂直叠置区域的晶闸管和控制栅极。 控制栅极可以与一个或多个晶闸管电耦合，并且可以可操作地耦合到电压源。 基于晶闸管的存储单元可以形成为阵列中的导电带，其可以用作阴极或数据线。 可以通过将半导体器件与诸如互补金属氧化物半导体（CMOS）器件的一个或多个存储器访问器件或常规逻辑器件集成来形成系统。

公开(公告)号：US09048131B2

公开(公告)日：2015-06-02

申请号：US14289162

申请日：2014-05-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: G11C11/34 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。