公开(公告)号：US08385018B2

公开(公告)日：2013-02-26

申请号：US12611294

申请日：2009-11-03

Applicant: Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

Inventor： Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

IPC: G11B5/265

CPC classification number: G11B5/3116 ,  G11B5/17 ,  G11B5/23 ,  G11B5/265 ,  G11B5/2652 ,  G11B5/59638

Abstract: A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.

Abstract translation: 根据一个实施例的磁性装置包括通量源; 耦合到磁通源的磁极，所述磁极具有两个或更多个间隙; 以及朝向所述间隙中的至少一个定位的低磁阻路径，并且朝向所述间隙中的至少另一个定位，以在所述通量源产生磁通时影响形成在所述至少一个间隙处的磁场。 其他公开的实施例包括具有在磁轭中具有不均匀布置的线圈匝的装置，用于在写入期间改变在至少一个间隙处形成的磁场。 在另外的实施例中，靠近或在其中一个间隙处的磁极的几何形状不同于磁极在靠近或另一个间隙处的几何形状，以帮助当磁通源产生磁通时在间隙处形成的场均衡。

公开(公告)号：US20120292779A1

公开(公告)日：2012-11-22

申请号：US13111283

申请日：2011-05-19

Applicant: MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

Inventor： MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

Abstract: A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

Abstract translation: 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US20110108958A1

公开(公告)日：2011-05-12

申请号：US12614062

申请日：2009-11-06

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L23/48 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.

Abstract translation: 一种结构包括具有顶部晶片表面的晶片。 晶片限定开口。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 晶片具有第一基准方向的厚度。 该结构还包括形成在开口中的贯通晶片通孔。 当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。 贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。 还公开了制造技术。

公开(公告)号：US07362582B2

公开(公告)日：2008-04-22

申请号：US11151905

申请日：2005-06-14

Applicant: John P. Karidis ,  Mark D. Schultz ,  Bucknell C. Webb

Inventor： John P. Karidis ,  Mark D. Schultz ,  Bucknell C. Webb

IPC: H05K7/20

CPC classification number: H01L23/433 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure for cooling an electronic device is disclosed. The structure includes a compressible top layer disposed over the electronic device. The structure further includes a plurality of rigid elements disposed between the top layer and the electronic device for providing a heat path from the electronic device and wherein the plurality of rigid elements provide mechanical compliance. In another alternative, the structure further includes a conformable heat-conducting layer disposed over the electronic device, wherein a bottom end of the plurality of rigid elements is coupled to the conformable heat-conducting layer.

Abstract translation: 公开了一种用于冷却电子设备的结构。 该结构包括设置在电子设备上的可压缩顶层。 该结构还包括设置在顶层和电子设备之间的多个刚性元件，用于提供来自电子设备的热路径，并且其中多个刚性元件提供机械顺应性。 在另一替代方案中，结构还包括设置在电子设备上的适形导热层，其中多个刚性元件的底端联接到适形导热层。

公开(公告)号：US07268963B2

公开(公告)日：2007-09-11

申请号：US10903153

申请日：2004-07-30

Applicant: Timothy J. Chainer ,  Mark D. Schultz ,  Bucknell C. Webb

Inventor： Timothy J. Chainer ,  Mark D. Schultz ,  Bucknell C. Webb

IPC: G11B5/09 ,  G11B21/02 ,  G11B5/596

CPC classification number: G11B5/59633 ,  G11B5/59605

Abstract: Self-servo-writing of multi-slot timing patterns is described. Individual timing marks are replaced with groups of timing mark slots. At each timing mark location, a time measurement is made by detecting a timing mark in one of the slots. Also, extensions to the existing timing marks are written in other slots. The combination of timing measurements at every timing mark and extensions to those timing marks written at every opportunity improves the overall precision of the timing propagation. The improved accuracy of timing mark placement produces a commensurate improvement in the placement of the concomitantly written servo-data. In addition, the alignment accuracy of the written pattern is less sensitive to variations in rotation speed and variations in the shape of written transitions. Moreover, only a single disk revolution is required at each servo radius to write servo data and propagate the timing marks to maintain timing alignment.

Abstract translation: 描述了多时隙定时模式的自伺服写入。 单个定时标记被定时标记位置组替换。 在每个定时标记位置，通过检测其中一个时隙中的定时标记来进行时间测量。 此外，现有时序标记的扩展也写在其他插槽中。 每个定时标记的定时测量和在每个机会上写入的定时标记的扩展的组合可以提高定时传播的总体精度。 定时标记放置的改进精度在同时写入的伺服数据的位置上产生相应的改进。 此外，写入的图案的对准精度对旋转速度的变化和写入的转变的形状的变化较不敏感。 此外，在每个伺服半径处仅需要一次盘旋转以写入伺服数据并传播定时标记以保持定时对准。

公开(公告)号：US06633451B1

公开(公告)日：2003-10-14

申请号：US09426435

申请日：1999-10-25

Applicant: Timothy J. Chainer ,  Bucknell C. Webb ,  Mark D. Schultz ,  Edward J. Yarmchuk

Inventor： Timothy J. Chainer ,  Bucknell C. Webb ,  Mark D. Schultz ,  Edward J. Yarmchuk

IPC: G11B2102

CPC classification number: G11B5/59633

Abstract: A method is provided for writing a servo-pattern on a storage medium. According to the method, first timing marks are written at a first radial position of the storage medium, and the head is moved to a second radial position. Time intervals between selected pairs of the first timing marks are measured, and other timing marks are written at the second radial position of the storage medium. The measuring step is performed after the moving step. In one preferred method, the steps of moving, measuring, and writing other timing marks are repeated until the servo-pattern is written on an entire surface of the storage medium. A method is also provided for generating an initial aligned pattern of timing marks for self-servo-writing on a storage medium.

Abstract translation: 提供一种用于将伺服图案写入存储介质的方法。 根据该方法，将第一定时标记写入存储介质的第一径向位置，并且将头移动到第二径向位置。 测量所选择的第一定时标记对之间的时间间隔，并且其他定时标记被写入存储介质的第二径向位置。 测量步骤在移动步骤之后进行。 在一个优选的方法中，重复移动，测量和写入其它定时标记的步骤，直到伺服图案被写入存储介质的整个表面。 还提供了一种用于在存储介质上产生用于自伺服写入的定时标记的初始对准图案的方法。

公开(公告)号：US5844742A

公开(公告)日：1998-12-01

申请号：US735924

申请日：1996-10-24

Applicant: Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

Inventor： Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

IPC: G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10 ,  G11B5/02

CPC classification number: G11B5/5534 ,  G11B21/10 ,  G11B21/106 ,  G11B5/59633 ,  G11B5/59644

Abstract: During a write revolution of a storage medium, a transition is written on the storage medium while servoing on another transition previously recorded on the storage medium. During that write revolution, a position error signal corresponding to the position error of the transducer relative to the previously recorded transition is determined. That position error signal is then stored, during the write revolution, to be used in computing a reference track value associated with the transition being written in order to correct for the position error

Abstract translation: 在存储介质的写入转动期间，在先前记录在存储介质上的另一个转换上进行伺服处理，在存储介质上写入转换。 在该写入旋转期间，确定对应于换能器相对于先前记录的转变的位置误差的位置误差信号。 然后，在写入旋转期间，存储该位置误差信号以用于计算与被写入的转换相关联的参考轨迹值，以便校正位置误差

公开(公告)号：US08801352B2

公开(公告)日：2014-08-12

申请号：US13207609

申请日：2011-08-11

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L21/00

CPC classification number: H01L21/67132

Abstract: Pick and place tape release techniques and tools that allow thin, fragile semiconductor dies to be removed from wafer tape with reduced tape release forces applied to the semiconductor dies. For example, a method for removing semiconductor die from wafer tape includes mounting a wafer ring having wafer tape and one or more dies attached to the wafer tape, and aligning an ejector pin assembly under a target die to be removed from the wafer tape. The ejector pin assembly includes a vacuum housing, an ejector pin, a suction plate, and an aperture formed in the suction plate in alignment with the ejector pin. A vacuum is generated in the vacuum housing to draw the tape against a surface of the suction plate. The ejector pin is extended through the vacuum housing out from the aperture of the suction plate to push against a backside of the target die and release the tape from the backside of the target die, and as the tape is released from the backside of the target die, the tape is drawn down against the suction plate by suction force of the vacuum.

Abstract translation: 拾取和放置磁带释放技术和工具，其允许薄的，脆弱的半导体管芯从晶片带去除，同时减小施加到半导体管芯上的剥离力。 例如，从晶片带除去半导体管芯的方法包括安装具有晶片带的晶片环和安装在晶片带上的一个或多个管芯，以及使靶组件下方的顶针组件对准晶片带。 顶针组件包括真空壳体，顶针，吸板和形成在吸板中的与顶针对准的孔。 在真空壳体中产生真空以将带材吸附在吸盘的表面上。 顶针从吸板的孔径延伸穿过真空壳体，以推压目标管芯的背面并从目标管芯的背面释放带，并且当带从靶的背面释放时 模具，胶带通过真空的吸力被吸引到吸盘上。

公开(公告)号：US08736277B2

公开(公告)日：2014-05-27

申请号：US13369872

申请日：2012-02-09

Applicant: Dennis G. Manzer ,  Bucknell C. Webb

Inventor： Dennis G. Manzer ,  Bucknell C. Webb

IPC: G01R31/06

CPC classification number: H01F38/00 ,  H01F2038/006

Abstract: Systems, methods and devices directed to transformers are disclosed. One transformer system includes a set of transformer cells and a controller. The set of transformer cells is coupled in series to form a series coupling, where each transformer cell includes at least one first coil and at least one second coil. The second coil is configured to receive electrical energy from the first coil through magnetic interaction. The controller is configured to modify electrical aspects at ends of the series coupling by independently driving the transformer cells such that at least one of the transformer cells is driven differently from at least one other transformer cell in the set.

Abstract translation: 公开了涉及变压器的系统，方法和装置。 一个变压器系统包括一组变压器单元和一个控制器。 该组变压器单元串联耦合以形成串联耦合，其中每个变压器单元包括至少一个第一线圈和至少一个第二线圈。 第二线圈被配置为通过磁相互作用从第一线圈接收电能。 控制器被配置为通过独立地驱动变压器单元来修改串联耦合的端部处的电气方面，使得变压器单元中的至少一个与组中的至少一个其它变压器单元不同地被驱动。

公开(公告)号：US20140061853A1

公开(公告)日：2014-03-06

申请号：US13597412

申请日：2012-08-29

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01F5/00 ,  H01L21/02 ,  H01L29/86

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.

Abstract translation: 提供具有层压的磁 - 绝缘体堆叠结构的诸如电感器，变压器等的半导体集成磁性器件，其中使用电镀技术形成层叠的磁性 - 绝缘体堆叠结构。 例如，集成层叠磁性装置包括在基板上形成交替的磁性层和绝缘层的多层堆叠结构，其中多层堆叠结构中的每个磁性层通过绝缘层与多层堆叠结构中的另一磁性层分离，以及 局部短路结构，以将多层堆叠结构中的每个磁性层电连接到多层堆叠结构中的下面的磁性层，以便利用叠层中的下面的导电层（磁性或种子层）作为电阴极来促进磁性层的电镀 /阳极，用于堆叠结构中的每个电镀磁性层。