公开(公告)号：US08507909B2

公开(公告)日：2013-08-13

申请号：US13308523

申请日：2011-11-30

Applicant: Ra-Min Tain ,  Ming-Ji Dai ,  Shyh-Shyuan Sheu ,  Chih-Sheng Lin ,  Shih-Hsien Wu

Inventor： Ra-Min Tain ,  Ming-Ji Dai ,  Shyh-Shyuan Sheu ,  Chih-Sheng Lin ,  Shih-Hsien Wu

IPC: H01L23/58

CPC classification number: G01B7/18 ,  G01L1/18 ,  G01L1/2206 ,  H01L2224/16145

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Abstract translation: 提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。 第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。 第一电路层设置在第一表面上。 第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。 第二电路层设置在第二表面上。 第一加热器包括串联连接以产生热量的多个第一开关。

公开(公告)号：US08219340B2

公开(公告)日：2012-07-10

申请号：US12435311

申请日：2009-05-04

Applicant: Keng-Li Su ,  Chih Sheng Lin ,  Chih-Wen Hsiao

Inventor： Keng-Li Su ,  Chih Sheng Lin ,  Chih-Wen Hsiao

IPC: G01R13/00 ,  G01R29/26

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.

Abstract translation: 提供了一种三维集成电路（3D IC）的通硅通孔（TSV）的监视方法，其中3D IC包括多个TSV，并且该方法包括：提供多个逆变器; 将变频器与TSV连接作为电路; 使电路振荡; 测量其中一个逆变器的输出端的输出信号; 以及基于输出信号确定3D IC的TSV的特性。

公开(公告)号：US20100176413A1

公开(公告)日：2010-07-15

申请号：US12685350

申请日：2010-01-11

Applicant: Chih-Sheng Lin ,  Che-Hsiung Wu

Inventor： Chih-Sheng Lin ,  Che-Hsiung Wu

IPC: H01L33/00 ,  H01L21/28

CPC classification number: H01L33/46 ,  H01L33/14 ,  H01L33/38

Abstract: A light-emitting diode device includes: a substrate; a light-emitting layered structure formed on the substrate; a multi-functional layer having a first main portion and formed on the light-emitting layered structure for spreading current laterally and for reflecting light emitted from the light-emitting layered structure; and first and second electrodes electrically coupled to the light-emitting layered structure. The first electrode is formed on the light-emitting layered structure and has a first electrode main part. The first main portion of the multi-functional layer is aligned below and is provided with a size larger than that of the first electrode main part.

Abstract translation: 发光二极管装置包括：基板; 形成在基板上的发光层状结构; 具有第一主要部分并形成在发光层状结构上用于横向扩散电流并用于反射从发光层状结构发射的光的多功能层; 以及电耦合到发光层状结构的第一和第二电极。 第一电极形成在发光层状结构上并具有第一电极主体部分。 多功能层的第一主要部分在下方对准并且具有比第一电极主体部分大的尺寸。

公开(公告)号：US20100153043A1

公开(公告)日：2010-06-17

申请号：US12435311

申请日：2009-05-04

Applicant: Keng-Li SU ,  Chih Sheng LIN ,  Chih-Wen HSIAO

Inventor： Keng-Li SU ,  Chih Sheng LIN ,  Chih-Wen HSIAO

IPC: G06F19/00 ,  G01R13/00

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.

Abstract translation: 提供了一种三维集成电路（3D IC）的通硅通孔（TSV）的监视方法，其中3D IC包括多个TSV，并且该方法包括：提供多个逆变器; 将变频器与TSV连接作为电路; 使电路振荡; 测量其中一个逆变器的输出端的输出信号; 以及基于输出信号确定3D IC的TSV的特性。

公开(公告)号：US07385866B2

公开(公告)日：2008-06-10

申请号：US11347052

申请日：2006-02-03

Applicant: Chih-Sheng Lin ,  Chia-Pao Chang ,  Jan-Ruei Lin

Inventor： Chih-Sheng Lin ,  Chia-Pao Chang ,  Jan-Ruei Lin

IPC: G11C7/02

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C7/14

Abstract: A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second switch, a second sub-array coupled to the cell input terminal through a third switch and coupled to the reference input terminal through a fourth switch, and a reference cell array coupled between the second switch and the fourth switch and coupled to the reference input terminal.

Abstract translation: 提供存储器件。 该器件包括具有单元输入端和参考输入端的读出放大器，通过第一开关耦合到单元输入端并通过第二开关耦合到参考输入端的第一子阵列，第二子阵列耦合 通过第三开关耦合到单元输入端，并通过第四开关耦合到参考输入端，以及耦合在第二开关和第四开关之间并耦合到参考输入端的参考单元阵列。

公开(公告)号：US6147361A

公开(公告)日：2000-11-14

申请号：US163383

申请日：1998-09-30

Applicant: Chih-Sheng Lin ,  Shun-Yi Lee

Inventor： Chih-Sheng Lin ,  Shun-Yi Lee

IPC: H01L23/544 ,  H01L23/58

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L2924/0002

Abstract: A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test stripes representative of the interconnection metallurgy used by the integrated circuits. The sensor capitalizes on the property of silicon whereby a small increase in temperature causes a large increase in carrier concentration. In this regard, the local temperature rise of an adjacent metal line undergoing EM failure manifests itself as a decrease in resistance of the sensor. The sensor is particularly suited for testing multi-level metallurgies such as those having an aluminum alloy sandwiched between metallic layers such as those used for diffusion barriers and anti-reflective coatings. Its fabrication is compatible with conventional MOSFET processes which use a self-aligned polysilicon gate. It can be particularly useful when built into the wafer kerf area or into a manufacturing test site(MTS) where it can be used to qualify the metallization of a particular job. Structures built into the wafer kerf can be tested immediately after metallization while those built into MTS chips can be reserved for long term reliability testing.

Abstract translation: 描述了一种多晶硅传感器，其可以并入到含有集成电路的硅晶片上，目的是检测和监测代表集成电路使用的互连冶金的金属测试条带中的电迁移（EM）。 该传感器利用硅的性质，其中温度的小的增加导致载流子浓度的大幅增加。 在这方面，经历EM故障的相邻金属线的局部温度升高本身就表现为传感器的电阻降低。 该传感器特别适用于测试多层次冶金，例如具有夹在金属层之间的铝合金的那些，例如用于扩散阻挡层和抗反射涂层的那些。 其制造与使用自对准多晶硅栅极的常规MOSFET工艺兼容。 当内置于晶圆切割区域或制造测试点（MTS）中时，特别有用，可用于对特定作业的金属化进行限定。 内置于晶圆切口的结构可以在金属化后立即进行测试，而内置于MTS芯片的结构可以保留用于长期可靠性测试。

公开(公告)号：US5627101A

公开(公告)日：1997-05-06

申请号：US566808

申请日：1995-12-04

Applicant: Chih-Sheng Lin ,  Shun-Yi Lee

Inventor： Chih-Sheng Lin ,  Shun-Yi Lee

IPC: G01R31/28 ,  H01L23/544 ,  H01L21/283 ,  H01L21/66

CPC classification number: G01R31/2858 ,  H01L22/34 ,  G01R31/2853 ,  H01L2924/0002 ,  Y10S438/927

Abstract: A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test stripes representative of the interconnection metallurgy used by the integrated circuits. The sensor capitalizes on the property of silicon whereby a small increase in temperature causes a large increase in carrier concentration. In this regard, the local temperature rise of an adjacent metal line undergoing EM failure manifests itself as a decrease in resistance of the sensor. The sensor is particularly suited for testing multi-level metallurgies such as those having an aluminum alloy sandwiched between metallic layers such as those used for diffusion barriers and anti-reflective coatings. Its fabrication is compatible with conventional MOSFET processes which use a self-aligned polysilicon gate. It can be particularly useful when built into the wafer kerf area or into a manufacturing test site(MTS) where it can be used to qualify the metallization of a particular job. Structures built into the wafer kerf can be tested immediately after metallization while those built into MTS chips can be reserved for long term reliability testing.

Abstract translation: 描述了一种多晶硅传感器，其可以并入到含有集成电路的硅晶片上，目的是检测和监测代表集成电路使用的互连冶金的金属测试条带中的电迁移（EM）。 该传感器利用硅的性质，其中温度的小的增加导致载流子浓度的大幅增加。 在这方面，经历EM故障的相邻金属线的局部温度升高本身就表现为传感器的电阻降低。 该传感器特别适用于测试多层次冶金，例如具有夹在金属层之间的铝合金的那些，例如用于扩散阻挡层和抗反射涂层的那些。 其制造与使用自对准多晶硅栅极的常规MOSFET工艺兼容。 当内置于晶圆切割区域或制造测试点（MTS）中时，特别有用，可用于对特定作业的金属化进行限定。 内置于晶圆切口的结构可以在金属化后立即进行测试，而内置于MTS芯片的结构可以保留用于长期可靠性测试。

公开(公告)号：US08314434B2

公开(公告)日：2012-11-20

申请号：US12968589

申请日：2010-12-15

Applicant: Chih-Sheng Lin ,  Shun-Hong Zheng

Inventor： Chih-Sheng Lin ,  Shun-Hong Zheng

IPC: H01L33/00

CPC classification number: H01L27/153 ,  H01L33/20 ,  H01L2224/18

Abstract: A light emitting diode module includes a substrate, at least two spaced apart light emitting diodes formed on the substrate, an insulating layer, and an electrically conductive layer. Each of the light emitting diodes includes a light emitting unit, an n-electrode, and a p-electrode. The light emitting unit has first and second portions. The first portion has an n-type top face and a first stepped side. The second portion has a p-type top face and a second stepped side. The insulating layer is formed on the n-type top face and the first stepped side of the first portion of one of the light emitting diodes, and the second stepped side and the p-type top face of the second portion of the other one of the light emitting diodes. The electrically conductive layer is formed on the insulating layer. A method of making the light emitting diode module is also disclosed.

Abstract translation: 发光二极管模块包括衬底，形成在衬底上的至少两个间隔开的发光二极管，绝缘层和导电层。 每个发光二极管包括发光单元，n电极和p电极。 发光单元具有第一和第二部分。 第一部分具有n型顶面和第一台阶侧。 第二部分具有p型顶面和第二阶梯侧。 绝缘层形成在一个发光二极管的第一部分的n型顶面和第一台阶侧，另一个的第二部分的第二台阶侧和p型顶面 发光二极管。 导电层形成在绝缘层上。 还公开了制造发光二极管模块的方法。

公开(公告)号：US08164113B2

公开(公告)日：2012-04-24

申请号：US12564051

申请日：2009-09-22

Applicant: Chih-Sheng Lin ,  Chih-Wen Hsiao ,  Keng-Li Su

Inventor： Chih-Sheng Lin ,  Chih-Wen Hsiao ,  Keng-Li Su

IPC: H01L23/60 ,  H01L29/74 ,  H01L31/111 ,  H01L23/62 ,  H01L23/48 ,  H02H9/00

CPC classification number: H01L23/60 ,  H01L23/481 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0251 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.

Abstract translation: 提供了一种三维（3D）集成电路（IC）穿硅通孔（TSV）器件的静电放电（ESD）结构。 ESD结构包括衬底，通过衬底形成并等效于电阻 - 电感 - 电容（RLC）器件的TSV器件，以及至少一个ESD器件，其被布置在衬底中并电连接到 TSV设备。 ESD结构可以保护3D IC TSV器件。

公开(公告)号：US07894274B2

公开(公告)日：2011-02-22

申请号：US12479612

申请日：2009-06-05

Applicant: Chih Sheng Lin ,  Min-Chuan Wang ,  Chih-Wen Hsiao ,  Keng-Li Su

Inventor： Chih Sheng Lin ,  Min-Chuan Wang ,  Chih-Wen Hsiao ,  Keng-Li Su

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C7/12 ,  G11C11/1655 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009

Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Abstract translation: 提供具有改善的写入电流的存储器，包括位线，写入开关和控制电路。 写开关耦合在电压源和位线之间，并且具有控制端子。 基于位线选择信号，控制电路控制写入开关的电导，并对写入开关的寄生电容器进行放电/充电。 在写开关的控制端达到预定电压电平之后，电压源接通。