公开(公告)号：US5237188A

公开(公告)日：1993-08-17

申请号：US798098

申请日：1991-11-27

Applicant: Hiroshi Iwai ,  Toyota Morimoto ,  Hisayo S. Momose ,  Kikuo Yamabe ,  Yoshio Ozawa

Inventor： Hiroshi Iwai ,  Toyota Morimoto ,  Hisayo S. Momose ,  Kikuo Yamabe ,  Yoshio Ozawa

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66575 ,  H01L21/28211

Abstract: A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.

Abstract translation: 一种形成在硅衬底上的半导体器件，包括在硅衬底上制造氧化硅膜的步骤，在氧化硅膜上产生薄氮化硅膜，在氮气气氛中对氮化硅膜进行氮化，产生 氮化硅膜上的导电膜在氮气气氛中氮化，从硅氧化膜，氮化硅膜和导电膜产生栅极区，沟道区位于硅衬底的栅极区下方， 在所述硅衬底中邻近所述沟道区的一侧产生源极区，在所述硅衬底中与所述沟道区的另一侧相邻的漏极区产生，并且在所述源极区，所述漏极区和所述栅极上产生布线区 地区。

公开(公告)号：US5073813A

公开(公告)日：1991-12-17

申请号：US557716

申请日：1990-07-26

Applicant: Shigeru Morita ,  Kikuo Yamabe ,  Masakazu Kakumu

Inventor： Shigeru Morita ,  Kikuo Yamabe ,  Masakazu Kakumu

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/768

Abstract: A MOS structure is formed on a silicon semiconductor substrate surface using a first gate electrode film made of polysilicon, an element isolation groove reaching the inside of the silicon semiconductor substrate is formed, and an insulating film is filled in the groove. In addition, a second gate electrode film made of a refractory metal such as molybdenum silicide is formed to be connected to the first gate electrode film, and the first and second gate electrode films are simultaneously removed to form a MOS gate electrode and a wiring layer.

Abstract translation: 使用由多晶硅制成的第一栅极电极膜，在硅半导体衬底表面上形成MOS结构，形成到硅半导体衬底内部的元件隔离沟，并且将绝缘膜填充到沟槽中。 此外，形成由诸如硅化钼的难熔金属制成的第二栅极电极膜，以连接到第一栅极电极膜，并且同时去除第一和第二栅极电极膜以形成MOS栅电极和布线层 。

公开(公告)号：US08034179B2

公开(公告)日：2011-10-11

申请号：US12865969

申请日：2009-02-06

Applicant: Yoshiro Kabe ,  Junichi Kitagawa ,  Kikuo Yamabe

Inventor： Yoshiro Kabe ,  Junichi Kitagawa ,  Kikuo Yamabe

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/3105 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/45565 ,  C23C16/511 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/28008 ,  H01L21/31612 ,  H01L21/31654 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66765

Abstract: In order to form an insulating film, which constitutes a flat interface with silicon, by CVD, a surface of silicon is oxidized to form a silicon oxide film using a plasma treatment apparatus in which microwaves are introduced into a chamber through a flat antenna having a plurality of holes. A silicon oxide film is formed as an insulating film on the silicon oxide film by CVD. Further, in the plasma treatment apparatus, a treating gas containing a noble gas and oxygen is introduced into the chamber, and, further, microwaves are introduced into the chamber through the flat antenna. Plasma is generated under a pressure in the range of not less than 6.7 Pa and not more than 533 Pa to modify the insulating film with the plasma.

Abstract translation: 为了通过CVD形成与硅形成平坦界面的绝缘膜，使用等离子体处理装置将硅的表面氧化形成氧化硅膜，其中微波通过具有 多个孔。 通过CVD在氧化硅膜上形成氧化硅膜作为绝缘膜。 此外，在等离子体处理装置中，将含有惰性气体和氧气的处理气体引入室内，并且还通过平板天线将微波引入室内。 在不低于6.7Pa且不大于533Pa的压力下产生等离子体，以便用等离子体改性绝缘膜。

公开(公告)号：US5885905A

公开(公告)日：1999-03-23

申请号：US582975

申请日：1996-01-04

Applicant: Souichi Nadahara ,  Kikuo Yamabe ,  Hideyuki Kobayashi ,  Kunihiro Terasaka ,  Akihito Yamamoto ,  Naohiko Yasuhisa

Inventor： Souichi Nadahara ,  Kikuo Yamabe ,  Hideyuki Kobayashi ,  Kunihiro Terasaka ,  Akihito Yamamoto ,  Naohiko Yasuhisa

IPC: H01L21/223 ,  C30B33/00 ,  H01L21/322 ,  H01L21/324 ,  H01L21/477

CPC classification number: C30B29/06 ,  C30B33/00 ,  H01L21/3225 ,  Y10S438/909

Abstract: A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before said heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree.0 C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.

Abstract translation: 一种处理半导体衬底的方法包括在气氛下对半导体衬底进行热处理的步骤。 该方法包括在非氧化性气氛下对半导体衬底进行不低于1100℃的热处理的步骤，其中在加热处理温度和热量下施加所述加热处理之前的热处理 处理时间落在由连接（900℃，4分钟），（800℃，40分钟），（700℃，11小时）和（600℃）四个点 ，320小时），其中热处理温度绘制在横坐标上，热处理时间绘制在图的纵坐标上。

公开(公告)号：US5543334A

公开(公告)日：1996-08-06

申请号：US356419

申请日：1994-12-15

Applicant: Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

Inventor： Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L2924/0002

Abstract: A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.

Abstract translation: 一种半导体器件的屏蔽方法。 制备在栅氧化膜上形成栅电极的硅晶片。 绝缘层沉积在硅晶片上。 待测试的一组晶体管的栅电极部分露出。 在具有暴露的栅电极的硅晶片上沉积导电层。 导电层被图案化为布线层，使得一组晶体管的栅电极可以彼此电连接。 用足够强度的光照射要测试的芯片面积，以在阱和衬底之间的耗尽层中产生所需量的载流子。 在光照射期间，在布线层和硅晶片的基板之间施加预定的测试电压，以测量流过布线层和栅氧化膜的电流。 可以基于测量的电流值来检测栅氧化膜的异常。 筛选方法可以在形成栅电极的完成之前进行。 此外，用户不使用的栅电极部分可以不与要使用的栅电极部分电连接。

公开(公告)号：US5354710A

公开(公告)日：1994-10-11

申请号：US17449

申请日：1993-02-12

Applicant: Hideichi Kawaguchi ,  Yoshitaka Tsunashima ,  Kikuo Yamabe ,  Katsuya Okumura

Inventor： Hideichi Kawaguchi ,  Yoshitaka Tsunashima ,  Kikuo Yamabe ,  Katsuya Okumura

IPC: H01L21/225 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/00 ,  H01L21/02 ,  H01L21/385

CPC classification number: H01L27/10861 ,  H01L21/2256 ,  H01L29/66181 ,  Y10S438/923

Abstract: A method of manufacturing semiconductor devices comprises the steps of preparing a semiconductor substrate having a surface and a natural oxide film on the surface, forming an adsorption enhancement layer on the surface of the semiconductor substrate, forming an impurity adsorption layer containing impurities on the adsorption enhancement layer, and thermally diffusing the impurities through the adsorption enhancement layer and the natural oxide film into the substrate.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：在表面上制备具有表面和自然氧化膜的半导体衬底，在半导体衬底的表面上形成吸附增强层，在吸附增强层上形成含有杂质的杂质吸附层 并且通过吸附增强层和天然氧化物膜将杂质热扩散到基底中。

公开(公告)号：US20100184267A1

公开(公告)日：2010-07-22

申请号：US12550788

申请日：2009-08-31

Applicant: Yoshiro Kabe ,  Junichi Kitagawa ,  Kikuo Yamabe

Inventor： Yoshiro Kabe ,  Junichi Kitagawa ,  Kikuo Yamabe

IPC: H01L21/316 ,  H01L21/762

CPC classification number: H01L21/31662 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/31654 ,  H01L21/67115 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: To form a good quality silicon oxide film provided with both a superior Qbd characteristic and Rd characteristic, a wafer W is loaded into a plasma treatment apparatus where the surface of a silicon layer 501 of the wafer W is treated by plasma oxidation to form on the silicon layer 501 to a film thickness T1 a silicon oxide film 503. Next, the wafer W on which the silicon oxide film 503 is formed is transferred to a thermal oxidation treatment apparatus where the silicon oxide film 503 is treated by thermal oxidation to thereby form a silicon oxide film 505 having a target film thickness T2.

Abstract translation: 为了形成具有优异的Qbd特性和Rd特性的优质氧化硅膜，将晶片W装载到等离子体处理装置中，其中通过等离子体氧化处理晶片W的硅层501的表面以形成在 硅层501形成膜厚T1，形成氧化硅膜503.接着，将形成有氧化硅膜503的晶片W转移到热氧化处理装置中，通过热氧化处理氧化硅膜503，形成 具有目标膜厚度T2的氧化硅膜505。

公开(公告)号：US06185472B2

公开(公告)日：2001-02-06

申请号：US08777189

申请日：1996-12-27

Applicant: Shinji Onga ,  Takako Okada ,  Hiroshi Tomita ,  Kikuo Yamabe ,  Haruo Okano

Inventor： Shinji Onga ,  Takako Okada ,  Hiroshi Tomita ,  Kikuo Yamabe ,  Haruo Okano

IPC: G06F1900

CPC classification number: H01L22/20 ,  G06F17/5018

Abstract: A semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them without testpieces is provided. The method includes the steps of collecting actually observed data during at least one of plural steps, obtaining prediction data in at least one of plural steps by using an ab initio molecular dynamics process simulator or a molecular dynamics simulator, comparing and verifying the prediction data and the actually observed data sequentially at real time, and correcting and processing the plural manufacturing process factors sequentially at real time if a difference in significance is recognized between set values for the plural manufacturing process factors and the plural manufacturing process factors estimated from the actually observed data according to comparison and verification.

Abstract translation: 提供一种能够根据预定时间表进行半导体器件制造工艺或在没有测试件的情况下对其进行校正的半导体器件制造方法。 该方法包括以下步骤：在多个步骤中的至少一个步骤中收集实际观察到的数据，通过使用从头分子动力学过程模拟器或分子动力学模拟器获得多个步骤中的至少一个步骤中的预测数据，比较和验证预测数据和 实际观察到的数据，并且如果在多个制造处理因子的设定值和从实际观测数据估计出的多个制造处理因子之间识别出显着性差异，则实时依次校正和处理多个制造工艺因素 根据比较和验证。

公开(公告)号：US5502010A

公开(公告)日：1996-03-26

申请号：US91266

申请日：1993-07-15

Applicant: Souichi Nadahara ,  Kikuo Yamabe ,  Hideyuki Kobayashi ,  Kunihiro Terasaka ,  Akihito Yamamoto ,  Naohiko Yasuhisa

Inventor： Souichi Nadahara ,  Kikuo Yamabe ,  Hideyuki Kobayashi ,  Kunihiro Terasaka ,  Akihito Yamamoto ,  Naohiko Yasuhisa

IPC: H01L21/223 ,  C30B33/00 ,  H01L21/322 ,  H01L21/324 ,  H01L21/477

CPC classification number: C30B29/06 ,  C30B33/00 ,  H01L21/3225 ,  Y10S438/909

Abstract: A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a high temperature heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before the high temperature heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree. C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.

Abstract translation: 一种处理半导体衬底的方法包括在气氛下对半导体衬底进行热处理的步骤。 该方法包括在非氧化性气氛下，在不低于1100℃的温度下对半导体衬底进行高温热处理的步骤，其中在加热到半导体衬底的高温热处理之前的热处理被加热 处理温度和热处理时间落入由连接（900℃，4分钟），（800℃，40分钟），（700℃，11小时）和（ 600℃，320小时），其中热处理温度绘制在横坐标上，热处理时间绘制在图的纵坐标上。

公开(公告)号：US5431561A

公开(公告)日：1995-07-11

申请号：US166014

申请日：1993-12-14

Applicant: Kikuo Yamabe ,  Keitaro Imai ,  Katsuya Okumura ,  Ken Nakao ,  Seikou Ueno

Inventor： Kikuo Yamabe ,  Keitaro Imai ,  Katsuya Okumura ,  Ken Nakao ,  Seikou Ueno

IPC: H01L21/324 ,  C30B31/12 ,  C30B31/14 ,  H01L21/22 ,  H01L21/31 ,  H01L21/673 ,  H01L21/683 ,  F27D5/00

CPC classification number: C30B31/12 ,  C30B31/14

Abstract: A method and an apparatus for heat treating in a heat treating apparatus having a heating chamber to be introduced with predetermined gas, a heater disposed around the heating chamber, and jigs disposed in the heating chamber for supporting wafers of a plurality of substrates to be treated in parallel with each other, wherein in order to make the temperature distribution of the wafers of the substrates to be treated in the radial direction uniform in the heat treatment, the jigs are formed to determine the sizes and the shape thereof in predetermined ranges having a gradient according to the heat treating method having a predetermined shape determining procedure so that the jigs are formed in ring-shaped trays (i.e. support-ring) for holding at the peripheries the substrates to be treated and the thickness of the tray is constant or such that the outer peripheral side thereof is thicker than the inner peripheral side thereof.

Abstract translation: 一种热处理装置中的热处理方法和装置，其特征在于，具有要加入预定气体的加热室，设置在所述加热室周围的加热器和设置在所述加热室中的夹具，用于支撑待处理的多个基板的晶片 彼此并联，其中为了使热处理中要处理的基板的晶片的温度分布均匀，形成夹具以确定其尺寸和形状，其具有在 根据具有预定形状确定步骤的热处理方法的梯度，使得夹具形成为环状托盘（即，支撑环），用于在周边保持要处理的基板，并且托盘的厚度等于或等于 其外周侧比其内周侧厚。