公开(公告)号：US06358758B2

公开(公告)日：2002-03-19

申请号：US09860386

申请日：2001-05-19

Applicant: Koji Arita ,  Shinichiro Hayashi ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

Inventor： Koji Arita ,  Shinichiro Hayashi ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

IPC: H01L2100

CPC classification number: H01L21/31691 ,  H01L27/10852

Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.

Abstract translation: 用于在集成电路中形成铁电体金属氧化物薄膜的液体前体包含超过化学计量平衡量的金属氧化物。 当前体包含用于形成铌酸铋钽酸铋的锶，铋，钽和铌时，前体含有过量的钽和铌中的至少一种。 含有由含有过量的钽和铌的前体制成的层状超晶格材料的薄膜的电容器在75℃下在1010个负极化开关脉冲之后和在125℃的109个负极化开关脉冲之后显示出良好的极化率和低百分比印记。

公开(公告)号：US06294438B1

公开(公告)日：2001-09-25

申请号：US09589520

申请日：2000-06-08

Applicant: Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

Inventor： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract translation: 一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

公开(公告)号：US06236076B1

公开(公告)日：2001-05-22

申请号：US09301867

申请日：1999-04-29

Applicant: Koji Arita ,  Carlos A. Paz de Araujo

Inventor： Koji Arita ,  Carlos A. Paz de Araujo

IPC: H01L2976

CPC classification number: H01L29/516 ,  H01L21/28291 ,  H01L28/56 ,  H01L29/78391

Abstract: A nonvolatile nondestructible read-out ferroelectric FET memory comprising a semiconductor substrate, a ferroelectric functional gradient material (“FGM”) thin film, and a gate electrode. In one basic embodiment, the ferroelectric FGM thin film contains a ferroelectric compound and a dielectric compound. The dielectric compound has a lower dielectric constant than the ferroelectric compound. There is a concentration gradient of the ferroelectric compound in the thin film. In a second basic embodiment, the FGM thin film is a functional gradient ferroelectric (“FGF”), in which compositional gradients of ferroelectric compounds result in unconventional hysteresis behavior. The unconventional hysteresis behavior of FGF thin films is elated to an enlarged memory window in ferroelectric FET memories. FGM thin films are preferably formed using a liquid source MOD methods, preferably a multisource CVD method.

Abstract translation: 包括半导体衬底，铁电功能梯度材料（“FGM”）薄膜和栅电极的非易失性非破坏性读出型铁电FET存储器。 在一个基本实施例中，铁电FGM薄膜含有铁电化合物和电介质化合物。 电介质化合物的介电常数比铁电化合物低。 在薄膜中存在铁电化合物的浓度梯度。 在第二基本实施例中，FGM薄膜是功能梯度铁电（“FGF”），其中铁电化合物的组成梯度导致非常规的滞后行为。 FGF薄膜的非常规滞后行为被激发到铁电FET存储器中的扩大的存储窗口。 FGM薄膜优选使用液体源MOD方法，优选多源CVD方法形成。

公开(公告)号：US06204111B1

公开(公告)日：2001-03-20

申请号：US09238157

申请日：1999-01-28

Applicant: Yasuhiro Uemoto ,  Eiji Fujii ,  Koji Arita ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Masamichi Azuma ,  Atsuo Inoue ,  Yasufumi Izutsu

Inventor： Yasuhiro Uemoto ,  Eiji Fujii ,  Koji Arita ,  Yoshihisa Nagano ,  Yasuhiro Shimada ,  Masamichi Azuma ,  Atsuo Inoue ,  Yasufumi Izutsu

IPC: H01L218242

CPC classification number: H01L27/11502 ,  H01L28/40 ,  H01L28/56

Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract translation: 一种用于制造用于集成电路的电容器的方法，包括以下步骤：在衬底上形成用于粘附层的钛膜，通过在离子注入氧离子之后将钛膜退火形成用于扩散阻挡层的二氧化钛膜 钛膜的表面区域，以将表面区域中的钛变为二氧化钛，并在二氧化钛膜上形成高介电常数电容器。

公开(公告)号：US6107657A

公开(公告)日：2000-08-22

申请号：US71121

申请日：1998-05-04

Applicant: Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

Inventor： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/72

CPC classification number: H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract translation: 一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

公开(公告)号：US5932281A

公开(公告)日：1999-08-03

申请号：US854173

申请日：1997-05-09

Applicant: Yukoh Hochido, deceased ,  Hidekimi Kadokura ,  Masamichi Matsumoto ,  Koji Arita ,  Masamichi Azuma ,  Tatsuo Otsuki

Inventor： Yukoh Hochido, deceased ,  Hidekimi Kadokura ,  Masamichi Matsumoto ,  Koji Arita ,  Masamichi Azuma ,  Tatsuo Otsuki

IPC: C23C16/40 ,  C23C18/12 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  B05D5/12 ,  B05D3/12 ,  C23C16/00

CPC classification number: H01L21/31691 ,  C23C16/40 ,  C23C18/1216 ,  C23C18/1279 ,  H01L28/56 ,  H01L28/55

Abstract: A method of forming a Bi-layered ferroelectric thin film on a substrate with good reproducibility, using a mixed composition of a Bi-containing organic compound and a metal polyalkoxide compound by at least one technique selected from the group consisting of molecular deposition such as CVD, and spincoat-sintering.

Abstract translation: 通过选自以下的至少一种技术，使用含Bi有机化合物和金属聚烷氧化物化合物的混合组合物，在复合性基板上形成双层铁电薄膜的方法， ，和旋涂烧结。

公开(公告)号：US5837591A

公开(公告)日：1998-11-17

申请号：US803144

申请日：1997-02-19

Applicant: Yasuhiro Shimada ,  Atsuo Inoue ,  Koji Arita ,  Toru Nasu ,  Yoshihisa Nagano ,  Akihiro Matsuda

Inventor： Yasuhiro Shimada ,  Atsuo Inoue ,  Koji Arita ,  Toru Nasu ,  Yoshihisa Nagano ,  Akihiro Matsuda

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/115 ,  H01L21/20

CPC classification number: H01L27/11502 ,  H01L28/40

Abstract: A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.

Abstract translation: 半导体器件包括其上形成有集成电路的硅衬底1，形成在硅衬底1上的第一绝缘层6，包括形成在第一绝缘层6上的下电极7的电容器，具有高介电常数的电介质膜8和上电极9 具有独立地引导到下电极7和上电极9的接触孔13的第二绝缘膜11，在接触孔13的底部接触下电极7和上电极9的扩散阻挡层17和形成在扩散阻挡层上的互连层15 在接触孔13的底部的扩散阻挡层17中，形成由粒状晶体构成的层状区域。

公开(公告)号：US5591663A

公开(公告)日：1997-01-07

申请号：US388502

申请日：1995-02-14

Applicant: Toru Nasu ,  Atsuo Inoue ,  Yoshihisa Nagano ,  Akihiro Matsuda ,  Koji Arita

Inventor： Toru Nasu ,  Atsuo Inoue ,  Yoshihisa Nagano ,  Akihiro Matsuda ,  Koji Arita

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L27/11502

Abstract: A manufacturing method of a semiconductor device comprises the steps:(a) forming a ferroelectric capacitor on a semiconductor substrate on which a MOS transistor is formed, (b) forming an interlayer insulating film which covers the whole semiconductor substrate, (c) forming first contact holes which reach diffusion layers of the MOS transistor, (d) after forming the first contact holes, providing a heat treatment in hydrogen atmosphere, (e) after the heat treatment, forming second contact holes which reach upper and lower electrodes of the ferroelectric capacitor on the interlayer insulating film, and (f) forming metal interconnection. Since the heat treatment in hydrogen atmosphere is provided before forming the second contact holes, a surface state density at interface between the semiconductor and a gate insulating film of the MOS transistor can be lowered without degrading the characteristics of ferroelectric capacitor.

Abstract translation: 半导体器件的制造方法包括以下步骤：（a）在形成有MOS晶体管的半导体衬底上形成强电介质电容器，（b）形成覆盖整个半导体衬底的层间绝缘膜，（c） 接触孔到达MOS晶体管的扩散层，（d）在形成第一接触孔之后，在氢气氛中进行热处理，（e）在热处理之后，形成到铁电体的上下电极的第二接触孔 层间绝缘膜上的电容器，（f）形成金属互连。 由于在形成第二接触孔之前提供氢气氛中的热处理，所以可以降低MOS晶体管的半导体与栅极绝缘膜之间的界面处的表面状态密度，而不降低铁电电容器的特性。

公开(公告)号：US4214925A

公开(公告)日：1980-07-29

申请号：US952160

申请日：1978-10-17

Applicant: Koji Arita ,  Masahiro Chiji ,  Takayoshi Asami ,  Yasuhumi Karaki ,  Toshihiko Endo

Inventor： Koji Arita ,  Masahiro Chiji ,  Takayoshi Asami ,  Yasuhumi Karaki ,  Toshihiko Endo

IPC: B21C37/22 ,  B23K1/00 ,  B23K1/19 ,  B23K31/02 ,  B23P15/26 ,  C22F1/04 ,  C22F1/05 ,  F28F1/30 ,  F28F3/02 ,  F28F3/08 ,  B27C1/00

CPC classification number: B23K1/0014 ,  B23K1/19 ,  B23P15/26 ,  C22F1/04 ,  C22F1/05 ,  F28F3/025 ,  B23K2201/14 ,  Y10T29/49378 ,  Y10T29/49393

Abstract: In a method for fabricating a brazed aluminum fin heat exchanger comprising a pair of brazing sheets each consisting of a core sheet and a cladding of brazing material disposed on either side of said core sheet and a corrugated fin interposed between the brazing sheets and brazed thereto, an improved process comprises making at least the fin of a heat-treatable (age-hardenable) aluminum alloy in the Al-Mg-Si system containing 0.15 to 0.4% copper, assembling the fin with said brazing sheets into a brazed aluminum fin heat exchanger unit, maintaining the heat exchanger unit at a temperature between 500.degree. C. and 570.degree. C. for a time from 30 minutes to 4 hours, quenching the solution-treated unit to room temperature under cooling conditions which provide a cooling rate between 2.8.degree. C./min. and 50.degree. C./min. down to 200.degree. C. and thereafter, age-hardening the quenched heat exchanger unit. The above heat-treatable aluminum alloy in the Al-Mg-Si system is AA 6951 or AA 6061.

Abstract translation: 在一种钎焊铝翅片热交换器的制造方法中，包括一对钎焊片，每一个钎焊片由芯片和布置在所述芯片的两侧的钎焊材料的包层和插入在钎焊片之间的波纹状散热片组成， 改进的方法包括在含有0.15-0.4％铜的Al-Mg-Si体系中至少制备可热处理（老化 - 硬化）铝合金的翅片，将所述钎焊片与所述钎焊片组装成钎焊铝翅片热交换器 单元，将热交换器单元维持在500℃至570℃的温度下30分钟至4小时，在冷却条件下将溶液处理单元淬火至室温，冷却速率为2.8℃ C./min。 和50℃/分钟。 低于200℃，此后对淬火的热交换器单元进行时效硬化。 Al-Mg-Si体系中的上述可热处理的铝合金是AA 6951或AA 6061。

公开(公告)号：US08563962B2

公开(公告)日：2013-10-22

申请号：US13515592

申请日：2010-11-17

Applicant: Koji Arita ,  Takumi Mikawa

Inventor： Koji Arita ,  Takumi Mikawa

IPC: H01L47/00

CPC classification number: G11C13/0007 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: Disclosed is a memory device provided with a plurality of memory cells and a lead-out line (12) shared among the memory cells. Each memory cell is provided with a transistor (6) formed above a substrate (1) and a variable resistance element (10) having a lower electrode (7), an upper electrode (9) that comprises a noble metal, and a variable resistance layer (8) disposed between the lower electrode (7) and the upper electrode (9). The resistance value of the variable resistance layer (8) changes reversibly in response to electric pulses that go through the transistor (6) and are applied between the lower electrode (7) and the upper electrode (9). The lead-out line (12) is in direct contact with the upper electrodes (9) of the memory cells.

Abstract translation: 公开了一种设置有多个存储单元和在存储单元之间共享的引出线（12）的存储器件。 每个存储单元设置有形成在基板（1）上方的晶体管（6）和具有下电极（7）的可变电阻元件（10），包含贵金属的上电极（9）和可变电阻 层（8）设置在下电极（7）和上电极（9）之间。 可变电阻层（8）的电阻值响应于通过晶体管（6）的电脉冲而可逆地改变并施加在下电极（7）和上电极（9）之间。 引出线（12）与存储单元的上电极（9）直接接触。