METHODS FOR ARRANGING NANOSCOPIC ELEMENTS WITHIN NETWORKS, FABRICS AND FILMS
    15.
    发明申请
    METHODS FOR ARRANGING NANOSCOPIC ELEMENTS WITHIN NETWORKS, FABRICS AND FILMS 审中-公开
    在网络,织物和膜中安装纳米元素的方法

    公开(公告)号:US20170072431A1

    公开(公告)日:2017-03-16

    申请号:US15241495

    申请日:2016-08-19

    申请人: Nantero inc.

    摘要: A method for arranging nanotube elements within nanotube fabric layers and films is disclosed. A directional force is applied over a nanotube fabric layer to render the fabric layer into an ordered network of nanotube elements. That is, a network of nanotube elements drawn together along their sidewalls and substantially oriented in a uniform direction. In some embodiments this directional force is applied by rolling a cylindrical element over the fabric layer. In other embodiments this directional force is applied by passing a rubbing material over the surface of a nanotube fabric layer. In other embodiments this directional force is applied by running a polishing material over the nanotube fabric layer for a predetermined time. Exemplary rolling, rubbing, and polishing apparatuses are also disclosed.

    摘要翻译: 公开了一种在纳米管织物层和膜内布置纳米管元件的方法。 在纳米管织物层上施加定向力以使织物层成为纳米管元件的有序网络。 也就是说,一个纳米管元件的网络沿其侧壁一起拉伸并且基本上沿均匀的方向取向。 在一些实施例中,通过将圆柱形元件滚动在织物层上而施加该定向力。 在其它实施例中,通过将摩擦材料通过纳米管织物层的表面来施加该定向力。 在其他实施例中,通过在纳米管织物层上运行抛光材料预定时间来施加该定向力。 还公开了示例性的滚动,摩擦和抛光装置。

    Methods for Forming Nanotube Fabric Layers with Increased Density
    16.
    发明申请
    Methods for Forming Nanotube Fabric Layers with Increased Density 审中-公开
    形成具有增加密度的纳米管织物层的方法

    公开(公告)号:US20170069846A1

    公开(公告)日:2017-03-09

    申请号:US15357003

    申请日:2016-11-21

    申请人: Nantero Inc.

    摘要: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.

    摘要翻译: 公开了在纳米管切换装置内钝化纳米管织物层以防止或以其他方式限制相邻材料层的侵蚀的方法。 在一些实施例中,将牺牲材料注入多孔纳米管织物层内以填充多孔纳米管织物层内的空隙,同时将一个或多个其它材料层施加在邻近纳米管织物层的位置。 一旦其它材料层就位,则去除牺牲材料。 在其他实施例中,使用非牺牲填充材料(以不损害纳米管织物层的切换功能的方式选择和沉积)在纳米管织物层内形成阻挡层。 在其他实施方案中,单个纳米管元素与纳米颗粒结合以限制纳米管织物层的孔隙率。

    METHODS FOR PROGRAMMING AND ACCESSING DDR COMPATIBLE RESISTIVE CHANGE ELEMENT ARRAYS
    17.
    发明申请
    METHODS FOR PROGRAMMING AND ACCESSING DDR COMPATIBLE RESISTIVE CHANGE ELEMENT ARRAYS 有权
    编程和访问DDR兼容电阻变化元件阵列的方法

    公开(公告)号:US20170032839A1

    公开(公告)日:2017-02-02

    申请号:US15191277

    申请日:2016-06-23

    申请人: Nantero Inc.

    IPC分类号: G11C13/00

    摘要: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

    摘要翻译: 公开了一种用于电阻变化元件阵列的高速存储器电路架构。 一组电阻变化元件组织成行和列,每列由字线和每行由两个位线提供服务。 每行电阻变化元件包括一对参考元件和读出放大器。 参考元件是电阻分量,其电阻值在对应于SET条件的电阻和对应于阵列中使用的电阻变化元件内的RESET条件的电阻之间。 通过通过字线选择的电阻变化元件排出一行位线中的一个,并同时对该行的位线中的另一个通过参考元件进行放电,并比较两条线上的放电速率来执行高速读操作 使用行的读出放大器。 存储状态数据作为高速同步数据脉冲被发送到输出数据总线。 从外部同步数据总线接收高速数据,并通过存储器阵列配置中的电阻变化元件内的PROGRAM操作存储高速数据。

    DDR compatible memory circuit architecture for resistive change element arrays
    19.
    发明授权
    DDR compatible memory circuit architecture for resistive change element arrays 有权
    用于电阻变化元件阵列的DDR兼容存储器电路架构

    公开(公告)号:US09412447B1

    公开(公告)日:2016-08-09

    申请号:US14812173

    申请日:2015-07-29

    申请人: Nantero Inc.

    IPC分类号: G11C11/00 G11C13/00

    摘要: A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.

    摘要翻译: 公开了一种用于电阻变化元件阵列的高速存储器电路架构。 一组电阻变化元件组织成行和列,每列由字线和每行由两个位线提供服务。 每行电阻变化元件包括一对参考元件和读出放大器。 参考元件是电阻分量,其电阻值在对应于SET条件的电阻和对应于阵列中使用的电阻变化元件内的RESET条件的电阻之间。 通过通过字线选择的电阻变化元件排出一行位线中的一个,并同时对该行的位线中的另一个通过参考元件进行放电,并比较两条线上的放电速率来执行高速读操作 使用行的读出放大器。 存储状态数据作为高速同步数据脉冲发送到输出数据总线。 从外部同步数据总线接收高速数据,并通过存储器阵列配置中的电阻变化元件内的PROGRAM操作存储高速数据。