公开(公告)号：US07902019B2

公开(公告)日：2011-03-08

申请号：US12098373

申请日：2008-04-04

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L21/8249

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20100136790A1

公开(公告)日：2010-06-03

申请号：US12591534

申请日：2009-11-23

Applicant: Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

Inventor： Chong-Kwang Chang ,  Hong-Jae Shin ,  Nae-In Lee ,  Kwang-Hyeon Baik ,  Seung-Il Bok ,  Hyo-Jeong Kim

IPC: H01L21/302

CPC classification number: H01L21/0337

Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Abstract translation: 一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个 第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻 掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第 第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层 他的间隔。

公开(公告)号：US20070117297A1

公开(公告)日：2007-05-24

申请号：US11656717

申请日：2007-01-23

Applicant: Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

Inventor： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC: H01L21/8234

CPC classification number: H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

Abstract: CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

Abstract translation: CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

公开(公告)号：US07037863B2

公开(公告)日：2006-05-02

申请号：US10659945

申请日：2003-09-10

Applicant: Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/00

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

公开(公告)号：US06998309B2

公开(公告)日：2006-02-14

申请号：US10786239

申请日：2004-02-24

Applicant: In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

Inventor： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11568 ,  Y10S438/954

Abstract: A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Abstract translation: 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US06917085B2

公开(公告)日：2005-07-12

申请号：US10728811

申请日：2003-12-08

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66598 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract translation: 本发明提供一种使用L形间隔物的半导体晶体管。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。 在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。 高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。 中等浓度接合区域位于高浓度和低浓度接合区域之间。

公开(公告)号：US06884705B2

公开(公告)日：2005-04-26

申请号：US10619581

申请日：2003-07-16

Applicant: Hwa Sung Rhee ,  Nae In Lee ,  Jung Il Lee ,  Sang Su Kim ,  Bae Geum Jong

Inventor： Hwa Sung Rhee ,  Nae In Lee ,  Jung Il Lee ,  Sang Su Kim ,  Bae Geum Jong

IPC: H01L21/8238 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/2807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/6659

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure. A method of manufacturing a semiconductor device having an HGSG comprises depositing a gate insulating layer over a surface of a semiconductor substrate, depositing a lower poly-SiGe layer having a columnar crystalline structure over the gate insulating layer, depositing an amorphous Si layer over the lower poly-SiGe layer, and crystallizing the amorphous Si layer to obtain an upper poly-Si layer having a random crystalline structure.

Abstract translation: 半导体器件包括杂质堆叠栅极（HGSG）。 该器件包括具有表面的半导体衬底，形成在半导体衬底的表面上的栅极绝缘层和形成在栅极绝缘层上的栅电极，其中栅极包括具有柱状晶体结构的下部多晶硅层 ，以及具有无规晶体结构的上部多晶硅层。 在一个实施例中，栅电极包括具有柱状晶体结构的下多晶SiGe层，具有无规晶体结构的中间层和具有柱状晶体结构的上多晶硅层。 制造具有HGSG的半导体器件的方法包括在半导体衬底的表面上沉积栅极绝缘层，在栅极绝缘层上沉积具有柱状晶体结构的下部多晶硅层，在下部 多晶SiGe层，并且使非晶Si层结晶，得到具有无规晶体结构的上多晶硅层。

公开(公告)号：US06875678B2

公开(公告)日：2005-04-05

申请号：US10650415

申请日：2003-08-29

Applicant: Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

Abstract translation: 可以将设置在硅基板上的由氧化铪，氧化锆，氧化铝，氧化钇和/或其它金属氧化物和硅酸盐的层形成的高介电层氮化并通过氧化，退火或氧化和退火的组合进行后热处理 以形成具有优异的迁移率和界面特性的高介电层。

公开(公告)号：US06524902B2

公开(公告)日：2003-02-25

申请号：US10001619

申请日：2001-10-23

Applicant: Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

Inventor： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

IPC: H01L218238

CPC classification number: H01L21/2807 ,  H01L21/823842

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

Abstract translation: 在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个 一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同 与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。 与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。 例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分Ge浓度低于10 ％。

公开(公告)号：US5852319A

公开(公告)日：1998-12-22

申请号：US953644

申请日：1997-10-17

Applicant: Young-sun Kim ,  Nae-in Lee ,  Dae-hong Ko

Inventor： Young-sun Kim ,  Nae-in Lee ,  Dae-hong Ko

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28052 ,  H01L29/4933 ,  Y10S257/90

Abstract: A gate electrode in a semiconductor device comprising; a gate oxide layer formed on a semiconductor substrate, a polysilicon layer formed on the gate oxide layer, a silicide layer formed on the polysilicon layer and, a metal silicide layer formed on the silicide layer.

Abstract translation: 一种半导体器件中的栅电极，包括： 形成在半导体衬底上的栅极氧化层，形成在栅极氧化层上的多晶硅层，形成在多晶硅层上的硅化物层和形成在硅化物层上的金属硅化物层。