公开(公告)号：US10733140B2

公开(公告)日：2020-08-04

申请号：US14727051

申请日：2015-06-01

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Arthur Joseph Hoane ,  Paul Hurtley

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F17/14 ,  G06F9/46

Abstract: A computer processor is disclosed. The computer processor may comprises a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that produce results with elements of widths different than that of the input elements. The computer processor may be implemented as a monolithic integrated circuit.

公开(公告)号：US10719451B2

公开(公告)日：2020-07-21

申请号：US15868513

申请日：2018-01-11

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  A. Joseph Hoane ,  Lei Wang ,  Gary Nacer ,  Aaron G. Milbury ,  Enrique A. Barria ,  Paul Hurtley

IPC: G06F12/1027 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/0864

Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

公开(公告)号：US20170025757A1

公开(公告)日：2017-01-26

申请号：US15141011

申请日：2016-04-28

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Sabin Daniel Iancu ,  Surducan Emanoil ,  Surducan Vasile

IPC: H01Q5/30 ,  H01Q9/04 ,  H01Q3/36 ,  H01Q1/24

CPC classification number: H01Q5/30 ,  H01Q1/243 ,  H01Q3/36 ,  H01Q3/38 ,  H01Q5/40 ,  H01Q9/0407 ,  H01Q9/0414 ,  H01Q21/0093 ,  H01Q21/065 ,  H01Q21/28 ,  H01Q23/00

Abstract: A monolithic dual band antenna is provided. The monolithic dual band antenna includes a first layer comprising a high frequency band antenna. The monolithic dual band antenna further includes a second layer underlying the first layer. The second layer includes a low frequency band antenna. The geometry of the high frequency antenna relative to the low frequency antenna causes resulting electric fields of the high frequency band antenna to be orthogonal to the resulting electric fields of the low frequency band antenna.

Abstract translation: 提供单片双频天线。 单片双频带天线包括包括高频带天线的第一层。 单片双频带天线还包括位于第一层下面的第二层。 第二层包括低频带天线。 高频天线相对于低频天线的几何形状导致高频带天线的所得电场与低频带天线的结果电场正交。

公开(公告)号：US20160314074A1

公开(公告)日：2016-10-27

申请号：US15087150

申请日：2016-03-31

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F9/30029 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3013 ,  G06F9/322 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602

Abstract: A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.

Abstract translation: 公开了实现虚拟地址的预翻译的计算机处理器。 计算机处理器可以包括包括一个或多个寄存器的寄存器文件。 计算机处理器可以包括处理逻辑。 处理逻辑可以接收一个值以存储在一个或多个寄存器的寄存器中。 处理逻辑可以将该值存储在寄存器中。 处理逻辑可以将接收的值指定为虚拟地址，虚拟地址具有对应的虚拟基页号。 处理逻辑可以将虚拟基页编号转换为对应的真实基页编号和对应于与虚拟基页编号相邻的零个或多个虚拟页码的零个或多个实际页号。 处理逻辑还可以在一个或多个寄存器的寄存器中存储真实的基页号码和零个或多个实际页码。

公开(公告)号：US20160224340A1

公开(公告)日：2016-08-04

申请号：US14724061

申请日：2015-05-28

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary J. Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Sitij Agrawal

IPC: G06F9/30

CPC classification number: G06F15/8053 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/461 ,  G06F9/462 ,  G06F15/7828 ,  G06F15/7839 ,  G06F15/8076 ,  G06F17/142

Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.

Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个复数运算指令对矢量寄存器堆中的变化数量的元件进行操作。 计算机处理器可以被实现为单片集成电路。

公开(公告)号：US20150220346A1

公开(公告)日：2015-08-06

申请号：US14539116

申请日：2014-11-12

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Shenghong Wang ,  C. John Glossner ,  Gary J. Nacer

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3826 ,  G06F9/3818 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/46

Abstract: A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.

Abstract translation: 计算设备确定具有发布序列的多个软件线程的当前软件线程在时钟周期期间不具有等待发送到硬件线程的第一指令。 计算设备识别发布序列中的一个或多个备选软件线程，其中有等待发出的指令。 考虑到在等待等待的指令中确定第二指令与任何其他指令没有任何依赖关系，计算设备在计算设备的时钟周期期间选择来自一个或多个替代软件线程中的第二软件线程的第二指令 发行。 鉴于从等待发布的每个指令提取的链接位的值，计算设备识别依赖关系。 计算设备向硬件线程发出第二条指令。

公开(公告)号：US20230358370A1

公开(公告)日：2023-11-09

申请号：US17790799

申请日：2020-12-29

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Sabin Daniel Iancu ,  John Glossner ,  Samantha Murphy ,  Kristin Koehn

IPC: F21K9/60 ,  H05B45/28

CPC classification number: F21K9/60 ,  H05B45/28 ,  F21Y2115/10

Abstract: A light-emitting diode (LED) lighting device includes a white light source characterized by a general color rendering index (CRI) value and a first color-specific CRI value, and one or more LED elements of a color light within a wavelength band, wherein a combined light source comprising the white light source and the one or more LED elements is characterized by the general CRI value and a second color-specific CRI value, and the second color-specific CRI value is greater than the first color-specific CRI value.

公开(公告)号：US11157407B2

公开(公告)日：2021-10-26

申请号：US15841974

申请日：2017-12-14

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  A. Joseph Hoane

IPC: G06F12/0817 ,  G06F9/30 ,  G06F12/084 ,  G06F12/0895 ,  G06F9/52 ,  G06F9/54 ,  G06F12/0811

Abstract: A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.

公开(公告)号：US20210319283A1

公开(公告)日：2021-10-14

申请号：US17351408

申请日：2021-06-18

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan MOUDGILL ,  John GLOSSNER

IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

Abstract: A system includes a processor and an accelerator circuit including an input circuit block comprising an input processor to perform first tasks of the neural network application, a filter circuit block comprising a filter processor to perform second tasks of the neural network application, and a plurality of general-purpose filters communicatively coupled to the input circuit block, the filter circuit block, where the input circuit block and the filter circuit block form stages of an execution pipeline, a producer stage is to supply data values to a consumer stage, and operation of the consumer stage is on hold until a start flag stored in a first general-purpose register of the plurality of general-purpose registers to be set by the producer stage.

公开(公告)号：US11144815B2

公开(公告)日：2021-10-12

申请号：US16769171

申请日：2018-12-03

Applicant: Optimum Semiconductor Technologies Inc.

Inventor： Mayan Moudgill ,  John Glossner

IPC: G06F9/38 ,  G06F15/76 ,  G06N3/04 ,  G06F9/30 ,  G06F9/32 ,  G06F15/78

Abstract: A system includes a memory, a processor, and an accelerator circuit. The accelerator circuit includes an internal memory, an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block to concurrently perform tasks of a neural network application assigned to the accelerator circuit by the processor.