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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    11.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20070087560A1

    公开(公告)日：2007-04-19

    申请号：US11251180

    申请日：2005-10-14

    Applicant: Jun-keun Kwak ,  Roland Hampp

    Inventor： Jun-keun Kwak ,  Roland Hampp

    IPC: H01L21/4763

    CPC classification number: H01L21/76846 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76895

    Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.

    Abstract translation: 提供一种制造具有增强的电气特性的半导体器件的方法。 该方法包括将衬底设置在处理室中的衬底支撑件上，预热衬底上的衬底，调节到300-400℃的温度达60秒以上，在衬底上形成硅保护层，通过 将硅源气体供应到处理室中，并加热调节至300-400℃温度的衬底支撑体上的衬底10秒以上，并在硅保护层上形成钨层。

    Methods of fabricating isolation regions of semiconductor devices and structures thereof
    12.
    发明授权
    Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
    制造半导体器件的隔离区域的方法及其结构

    公开(公告)号：US08936995B2

    公开(公告)日：2015-01-20

    申请号：US11365226

    申请日：2006-03-01

    Applicant: Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

    Inventor： Armin Tilke ,  Marcus Culmsee ,  Chris Stapelmann ,  Bee Kim Hong ,  Roland Hampp

    IPC: H01L21/762 ,  H01L21/77

    CPC classification number: H01L29/0649 ,  H01L21/02271 ,  H01L21/76229 ,  H01L21/76232

    Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

    Abstract translation: 公开了制造半导体器件的隔离区域的方法及其结构。 在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。 所述至少一个沟槽包括侧壁，底面，下部和上部。 第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。 第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。 第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。 第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。 第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

    Barrier for Copper Integration in the FEOL
    16.
    发明申请
    Barrier for Copper Integration in the FEOL 审中-公开
    铜在铜焊上的一体化障碍

    公开(公告)号：US20090218692A1

    公开(公告)日：2009-09-03

    申请号：US12040441

    申请日：2008-02-29

    Applicant: Roland Hampp

    Inventor： Roland Hampp

    IPC: H01L21/768 ,  H01L23/52

    CPC classification number: H01L23/485 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Copper integration in the FEOL stage is disclosed for a preliminary semiconductor device by forming a recess in a substrate of the device, the recess having a bottom surface and sidewall surfaces, depositing a barrier layer having about a 100% step coverage on the sidewall surfaces and the bottom surface, and depositing copper into the recess over the barrier layer to form a contact providing electrical connection to the preliminary semiconductor device.

    Abstract translation: 通过在器件的衬底中形成凹槽，凹部具有底表面和侧壁表面，在侧壁表面上沉积具有约100％阶梯覆盖的阻挡层，并且在侧壁表面上沉积具有约100％阶梯覆盖的势垒层， 底部表面，并且将铜沉积在阻挡层上的凹部中以形成提供与初级半导体器件的电连接的触点。

    Self Aligned Silicided Contacts
    17.
    发明申请
    Self Aligned Silicided Contacts 有权
    自对准硅胶接头

    公开(公告)号：US20120126343A1

    公开(公告)日：2012-05-24

    申请号：US13365418

    申请日：2012-02-03

    Applicant: Roland Hampp

    Inventor： Roland Hampp

    IPC: H01L29/78 ,  H01L29/41 ,  H01L29/45

    CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

    Abstract translation: 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。

    Methods of Forming Conductive Features and Structures Thereof
    18.
    发明申请
    Methods of Forming Conductive Features and Structures Thereof 审中-公开
    形成导电特性及结构的方法

    公开(公告)号：US20110175148A1

    公开(公告)日：2011-07-21

    申请号：US13074888

    申请日：2011-03-29

    Applicant: Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    Inventor： Jiang Yan ,  Roland Hampp ,  Jin-Ping Han ,  Manfred Eller ,  Alois Gutmann

    IPC: H01L29/772

    CPC classification number: H01L21/76804 ,  H01L21/823807 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a sacrificial material. A second material is formed over the first material and the sacrificial material, and a second pattern for an upper portion of the feature is formed in the second material. The sacrificial material is removed. The first pattern and the second pattern are filled with a third material.

    Abstract translation: 公开了形成特征及其结构的方法。 在一个实施例中，形成特征的方法包括在工件上形成第一材料，形成用于第一材料中特征的下部的第一图案，以及用牺牲材料填充第一图案。 在第一材料和牺牲材料上形成第二材料，并且在第二材料中形成用于特征的上部的第二图案。 牺牲材料被去除。 第一图案和第二图案填充有第三材料。

    Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups
    19.
    发明申请
    Threshold Voltage Consistency and Effective Width in Same-Substrate Device Groups 有权
    相同基板设备组中的阈值电压一致性和有效宽度

    公开(公告)号：US20090227086A1

    公开(公告)日：2009-09-10

    申请号：US12043384

    申请日：2008-03-06

    Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

    Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

    IPC: H01L21/76

    CPC classification number: H01L21/76262 ,  H01L21/76278

    Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

    Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

    Self Aligned Silicided Contacts
    20.
    发明申请
    Self Aligned Silicided Contacts 有权
    自对准硅胶接头

    公开(公告)号：US20090218640A1

    公开(公告)日：2009-09-03

    申请号：US12040409

    申请日：2008-02-29

    Applicant: Roland Hampp

    Inventor： Roland Hampp

    IPC: H01L29/78 ,  H01L23/48 ,  H01L21/3205

    CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

    Abstract translation: 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。

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