公开(公告)号：US20230207651A1

公开(公告)日：2023-06-29

申请号：US17561686

申请日：2021-12-23

申请人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Tahir GHANI ,  Tricia MEYER ,  Cory BOMBERGER ,  Glenn A. GLASS ,  Stephen M. CEA ,  Anant H. JAHAGIRDAR

发明人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Tahir GHANI ,  Tricia MEYER ,  Cory BOMBERGER ,  Glenn A. GLASS ,  Stephen M. CEA ,  Anant H. JAHAGIRDAR

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L29/78696 ,  H01L29/0673

摘要： Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.

公开(公告)号：US11037923B2

公开(公告)日：2021-06-15

申请号：US13538935

申请日：2012-06-29

申请人： Mark T. Bohr ,  Stephen M. Cea ,  Barbara A. Chappell

发明人： Mark T. Bohr ,  Stephen M. Cea ,  Barbara A. Chappell

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

摘要： Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

公开(公告)号：US09608059B2

公开(公告)日：2017-03-28

申请号：US13995418

申请日：2011-12-20

申请人： Annalisa Cappellani ,  Stephen M. Cea ,  Tahir Ghani ,  Harry Gomez ,  Jack T. Kavalieros ,  Patrick H. Keys ,  Seiyon Kim ,  Kelin J. Kuhn ,  Aaron D. Lilak ,  Rafael Rios ,  Mayank Sahni

发明人： Annalisa Cappellani ,  Stephen M. Cea ,  Tahir Ghani ,  Harry Gomez ,  Jack T. Kavalieros ,  Patrick H. Keys ,  Seiyon Kim ,  Kelin J. Kuhn ,  Aaron D. Lilak ,  Rafael Rios ,  Mayank Sahni

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/775 ,  H01L27/12 ,  B82Y10/00

CPC分类号： H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US09583602B2

公开(公告)日：2017-02-28

申请号：US15209552

申请日：2016-07-13

申请人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

发明人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

摘要翻译： 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。

公开(公告)号：US20160322480A1

公开(公告)日：2016-11-03

申请号：US15209552

申请日：2016-07-13

申请人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

发明人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/786 ,  H01L29/423

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US09224810B2

公开(公告)日：2015-12-29

申请号：US13996503

申请日：2011-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Annalisa Cappellani ,  Stephen M. Cea ,  Rafael Rios ,  Glenn A. Glass

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

摘要翻译： 描述了免费的金属氧化物半导体纳米线结构。 例如，半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点，并且在离散通道区域的任一侧上包括离散通道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

公开(公告)号：US20150325648A1

公开(公告)日：2015-11-12

申请号：US14803919

申请日：2015-07-20

申请人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

发明人： Stephen M. CEA ,  Annalisa CAPPELLANI ,  Martin D. GILES ,  Rafael RIOS ,  Seiyon KIM ,  Kelin J. KUHN

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/268

CPC分类号： H01L29/78618 ,  B82Y40/00 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

摘要翻译： 描述了具有非离散源极和漏极区域的纳米线结构。 例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。 每个纳米线包括设置在纳米线中的离散通道区域。 栅电极堆叠围绕多个垂直堆叠的纳米线。 一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

公开(公告)号：US09129829B2

公开(公告)日：2015-09-08

申请号：US14274592

申请日：2014-05-09

申请人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

发明人： Kelin J. Kuhn ,  Seiyon Kim ,  Rafael Rios ,  Stephen M. Cea ,  Martin D. Giles ,  Annalisa Cappellani ,  Titash Rakshit ,  Peter Chang ,  Willy Rachmady

IPC分类号： H01L29/165 ,  H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

公开(公告)号：US09129827B2

公开(公告)日：2015-09-08

申请号：US13976068

申请日：2012-04-13

申请人： Annalisa Cappellani ,  Van H. Le ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Stephen M. Cea

发明人： Annalisa Cappellani ,  Van H. Le ,  Glenn A. Glass ,  Kelin J. Kuhn ,  Stephen M. Cea

IPC分类号： H01L33/12 ,  H01L29/06 ,  H01L21/76 ,  H01L21/02 ,  H05K1/18 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

摘要： Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

摘要翻译： 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fe 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

公开(公告)号：US08957476B2

公开(公告)日：2015-02-17

申请号：US13722801

申请日：2012-12-20

申请人： Glenn A. Glass ,  Daniel B. Aubertine ,  Anand S. Murthy ,  Gaurav Thareja ,  Stephen M. Cea

发明人： Glenn A. Glass ,  Daniel B. Aubertine ,  Anand S. Murthy ,  Gaurav Thareja ,  Stephen M. Cea

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/16 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/785 ,  H01L29/7853

摘要： Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了与从硅（Si）到硅锗（SiGe）的薄晶体管元件的转换相关联的技术和配置。 在一个实施例中，一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底，沟道体包括硅，在沟道本体上形成包含锗的包覆层，并使通道体退火， 锗扩散到通道体内。 可以描述和/或要求保护其他实施例。