公开(公告)号：US20130168857A1

公开(公告)日：2013-07-04

申请号：US13616890

申请日：2012-09-14

Applicant: Thomas Matthew GREGORICH ,  Andrew C. CHANG ,  Tzu-Hung LIN

Inventor： Thomas Matthew GREGORICH ,  Andrew C. CHANG ,  Tzu-Hung LIN

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Abstract translation: 本发明提供一种模制插入器封装及其制造方法。 模制插入器封装包括多个金属螺柱。 模制材料封装离开暴露的金属螺柱的底表面的金属螺柱。 第一芯片设置在模制材料上，连接到金属螺柱的顶表面。 多个焊球连接并接触到金属螺柱的底表面。

公开(公告)号：US20130161810A1

公开(公告)日：2013-06-27

申请号：US13332658

申请日：2011-12-21

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/498

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 焊料电阻层设置在衬底上，具有覆盖第一导电迹线的一部分的延伸部分，其中阻焊层的延伸部分的宽度大于第一导电迹线部分的宽度。 半导体管芯设置在第一导电迹线上。

公开(公告)号：US08390119B2

公开(公告)日：2013-03-05

申请号：US13110932

申请日：2011-05-19

Applicant: Tzu-Hung Lin ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

IPC: H01L23/52

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract translation: 倒装芯片封装包括具有管芯附接表面的衬底; 以及安装在所述管芯附接表面上的管芯，其具有与所述衬底相对的所述管芯的有源表面，其中所述管芯经由所述有源表面上的多个铜柱凸起与所述衬底互连，其中所述多个铜柱中的至少一个 凸块具有基本上等于或小于衬底的芯片附接表面上的迹线的线宽的凸起宽度。

公开(公告)号：US20160180048A1

公开(公告)日：2016-06-23

申请号：US14975411

申请日：2015-12-18

Applicant: TZU-HUNG LIN

Inventor： Tzu-Hung LIN ,  Kuang-Lung KO ,  Chia-Cheng HUNG ,  Yi-Ning SU

IPC: G06F19/00 ,  H04L29/06

CPC classification number: G06F19/3418 ,  G16H10/60 ,  H04L63/083 ,  H04L63/102

Abstract: The present invention is to provide a cloud-based retrieval method of medical information and system thereof. The method comprises (a) generating an identification code corresponding to a personally identifiable information about a subject; (b) identifying a tested item for the subject to generate a medical information; (c) establishing a connection between the medical information and the subject; (d) submitting a retrieval request data including at least a part of personally identifiable information; (e) executing an algorithm to calculate the retrieval request data with respect to the personally identifiable information, and verifying the retrieval request matches with the personally identifiable information, and generating a subject-specific login password; and (f) verifying the subject-specific login password, and determining the medical information being accessible to the subject.

Abstract translation: 本发明是提供一种基于云的医疗信息检索方法及其系统。 该方法包括：（a）生成与关于对象的个人身份信息相对应的识别码; （b）识别该受试者的测试项目以产生医疗信息; （c）建立医疗信息与受试者之间的联系; （d）提交包括至少一部分个人身份信息的检索请求数据; （e）执行算法来计算关于个人身份信息的检索请求数据，以及验证检索请求与个人身份信息的匹配，以及生成特定主题的登录密码; 以及（f）验证所述特定主题登录密码，以及确定所述受试者可访问的所述医学信息。

公开(公告)号：US20130087911A1

公开(公告)日：2013-04-11

申请号：US13612764

申请日：2012-09-12

Applicant: Thomas Matthew GREGORICH ,  Tzu-Hung LIN

Inventor： Thomas Matthew GREGORICH ,  Tzu-Hung LIN

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip.

Abstract translation: 提供了一种集成电路（IC）封装结构，包括：第一集成电路（IC）封装，包括：具有相对的第一和第二表面的第一封装衬底，其中第一半导体芯片设置在第一 第一封装基板的表面。 此外，第二集成电路（IC）封装设置在与第一封装衬底的第一表面的第一部分不同的第二部分上，包括：具有相反的第三和第四表面的第二封装衬底，其中第二半导体 芯片设置在第二封装衬底的第三表面的一部分上，并且第二半导体芯片具有与第一半导体芯片的功能不同的功能。

公开(公告)号：US20120126368A1

公开(公告)日：2012-05-24

申请号：US13109740

申请日：2011-05-17

Applicant: Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

Inventor： Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

IPC: H01L29/02 ,  H01L23/488

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一钝化层设置在基板上。 凸块下金属层设置在第一钝化层上。 无源器件设置在凸块下金属层上

公开(公告)号：US20120032322A1

公开(公告)日：2012-02-09

申请号：US13110932

申请日：2011-05-19

Applicant: Tzu-Hung Lin ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

IPC: H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract translation: 倒装芯片封装包括具有管芯附接表面的衬底; 以及安装在所述管芯附接表面上的管芯，其具有与所述衬底相对的所述管芯的有源表面，其中所述管芯经由所述有源表面上的多个铜柱凸起与所述衬底互连，其中所述多个铜柱中的至少一个 凸块具有基本上等于或小于衬底的芯片附接表面上的迹线的线宽的凸起宽度。