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公开(公告)号：US20130312911A1
公开(公告)日：2013-11-28
申请号：US13660304
申请日：2012-10-25
Applicant: UNIMICRON TECHNOLOGY CORPORATION
Inventor： Tzyy-Jang Tseng , Tsung-Yuan Chen
CPC classification number: H01L21/6708 , H05K3/0085 , H05K2203/0746
Abstract: A supplying device including a supplying part and an adjustment part is provided. The supplying part includes a run-through supplying path for transporting a fluid. The adjustment part includes a channel and one or more recovery paths adjacent to the channel. The supplying part is disposed in the channel to allow the fluid to flow out of the channel through the supplying part and to allow the recovery paths to suck a portion of the etching solution outputted from the channel in order to control the amount of output of the fluid. Wet-etching equipment including the supplying device is also provided.
Abstract translation: 提供包括供给部和调整部的供给装置。 供给部包括用于输送流体的贯通供给路径。 调整部分包括通道和与通道相邻的一个或多个恢复路径。 供给部设置在通道中以允许流体通过供应部分流出通道，并且允许回收路径吸收从通道输出的一部分蚀刻溶液，以便控制输出的量 流体。 还提供了包括供应装置的湿蚀设备。
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公开(公告)号：US11825604B2
公开(公告)日：2023-11-21
申请号：US17529410
申请日：2021-11-18
Applicant: Unimicron Technology Corporation
Inventor： Ching-Ho Hsieh , Ming-Hsing Wu , Kuei-Sheng Wu
CPC classification number: H05K1/144 , H01R12/79 , H05K1/028 , H05K2201/042 , H05K2201/09063 , H05K2201/10189 , H05K2201/2018
Abstract: A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.
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公开(公告)号：US11408720B2
公开(公告)日：2022-08-09
申请号：US17209738
申请日：2021-03-23
Applicant: Unimicron Technology Corporation
Inventor： Cheng-Jui Chang , Hung-Lin Chang , Jeng-Wey Chiang
Abstract: A method for measuring thickness of dielectric layer in circuit board includes the following steps: First, circuit board including dielectric layer and circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes test area including test pattern and through hole. The test pattern includes first conductor and second conductors. The distance between the side of the through hole and the second conductor is less than the distance between the side of the through hole and the first conductor. Next, measuring device including conductive pin and sensing element is provided. Next, the conductive pin is powered, and one end of the conductive pin is electrically connected to the second conductor. Next, the sensing element is moved along the through hole to obtain sensing curve, and the thickness of the dielectric layer is calculated via variations of the sensing curve.
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14.发明申请公开(公告)号：US20210378092A1
公开(公告)日：2021-12-02
申请号：US16944178
申请日：2020-07-31
Applicant: UNIMICRON TECHNOLOGY CORPORATION
Inventor： YI LIN , HSIAO-HAN HUANG , YU-HSIN PAN
Abstract: Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
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公开(公告)号：US10820411B1
公开(公告)日：2020-10-27
申请号：US16879951
申请日：2020-05-21
Applicant: Unimicron Technology Corporation
Inventor： Shih-Lian Cheng , Zhe-Yong Lin , Li-Jie Liu , Ching Sheng Chen
Abstract: A manufacturing method for a circuit board and a circuit board are provided. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.
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Patent Agency Ranking
公开(公告)号：US09111818B2
公开(公告)日：2015-08-18
申请号：US14018757
申请日：2013-09-05
Applicant: Unimicron Technology Corporation
Inventor： Chun-Ting Lin , Yu-Chung Hsieh , Ying-Tung Wang , Ying-Chih Chan
CPC classification number: H01L24/13 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/11 , H01L24/16 , H01L2224/1132 , H01L2224/11422 , H01L2224/11462 , H01L2224/11464 , H01L2224/1161 , H01L2224/11622 , H01L2224/11823 , H01L2224/11825 , H01L2224/13017 , H01L2224/13019 , H01L2224/13022 , H01L2224/13026 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1357 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/1369 , H01L2224/16225 , H01L2224/16227 , H01L2224/81192 , H01L2924/351 , H01L2924/381 , H01L2924/3841 , H05K3/4007 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/00
Abstract: A packaging substrate is provided, including a substrate body having a plurality of conductive pads, an insulating protective layer formed on the substrate body for the conductive pads to be exposed therefrom, and a plurality of conductive pillars disposed on the conductive pads. Each of the conductive pillars has a bottom end and a top end narrower than the bottom end, thereby forming a cone-shaped structure that does not have a wing structure. Therefore, the distance between contact points is reduced and the demands for fine-pitch and multi-joints are satisfied.
Abstract translation: 提供一种封装基板，包括具有多个导电焊盘的基板主体，形成在基板主体上用于要暴露的导电焊盘的绝缘保护层，以及设置在导电焊盘上的多个导电柱。 每个导电柱具有比底端窄的底端和顶端，从而形成不具有翼结构的锥形结构。 因此，接触点之间的距离减小，满足细间距和多关节的要求。
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公开(公告)号：US09070616B2
公开(公告)日：2015-06-30
申请号：US14097656
申请日：2013-12-05
Applicant: Unimicron Technology Corporation
Inventor： Tzyy-Jang Tseng , Chung-W. Ho
IPC: H01L21/44 , H01L21/48 , H01L23/00 , H01L23/498
CPC classification number: H01L24/19 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/01029
Abstract: A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.
Abstract translation: 封装基板包括第一介电层; 多个第一导电焊盘，其嵌入并暴露于所述第一介电层的第一表面; 第一电路层，其被嵌入并暴露于所述第一介电层的第二表面; 设置在第一电介质层中的多个第一金属凸块，每个第一金属凸块具有嵌入在第一电路层中的第一端和与第一端相对的第二端并且设置在第一导电焊盘之一上，导电种子层 设置在第一电路层和第一电介质层之间以及第一电路层和第一金属凸块之间; 布置在第一电路层和第一介电层上的叠层结构; 以及设置在所述积层结构上的多个第二导电焊盘。 包装衬底具有改善的超翘曲问题。
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公开(公告)号：US20150129285A1
公开(公告)日：2015-05-14
申请号：US14602645
申请日：2015-01-22
Applicant: Unimicron Technology Corporation
Inventor： Dyi-Chung Hu , Tzyy-Jang Tseng
IPC: H01L23/498 , H05K1/11
CPC classification number: H05K3/4038 , H01L21/4846 , H01L21/76898 , H01L23/147 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/131 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/014 , H01L2924/15311 , H05K1/11 , H05K1/112 , H05K1/142 , H05K1/183 , H05K2201/10674 , Y10T29/4913 , Y10T29/49146 , Y10T29/49165
Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias. As such, the first end surfaces of the conductive through-vias of the through-via interposer are electrically connected to the redistribution layer to thereby be electrically connected to electrode pads of a semiconductor chip having smaller pitches, while the second end surfaces of the conductive through-vias electrically connect with conductive vias of the built-up structure having larger pitches, thereby allowing the packaging substrate to be coupled with the semiconductor chip having high-density circuits.
Abstract translation: 提供具有嵌入式通孔插入器的封装衬底，其包括密封剂层，嵌入密封层中的通孔插入件，并且其中具有多个导电通孔，重分布层嵌入密封层中并形成在 所述通孔插入件与所述导电通孔的第一端面电连接，以及形成在所述密封层和所述通孔插入件上的积层结构，用于电连接所述导电通孔的第二端面 。 因此，通孔插入器的导电通孔的第一端面电连接到再分配层，从而与具有较小间距的半导体芯片的电极焊盘电连接，而导电的第二端面 通孔与具有较大间距的积层结构的导电通孔电连接，从而允许封装衬底与具有高密度电路的半导体芯片耦合。
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公开(公告)号：US20150068033A1
公开(公告)日：2015-03-12
申请号：US14539312
申请日：2014-11-12
Applicant: Unimicron Technology Corporation
Inventor： Tzyy-Jang Tseng , Chung-W. Ho
CPC classification number: H05K3/0091 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/12042 , H01L2924/15311 , H05K3/4007 , H05K3/4647 , H05K3/4682 , H05K3/4685 , Y10T29/49155 , H01L2924/00
Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.
Abstract translation: 封装基板包括第一介电层，第一电路层，第一金属凸块和积层结构。 第一金属凸块和第一电路层嵌入并暴露于第一电介质层的两个表面。 第一金属凸块的端部嵌入在第一电路层中，并且在第一电路层和第一电介质层之间。 此外，导电种子层设置在第一电路层和第一金属凸块之间。 所述积层结构设置在所述第一电路层和所述第一电介质层上。 积层结构的最外层具有多个导电垫。 与现有技术相比，本发明可以有效地改善传统封装基板的翘曲问题。
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公开(公告)号：US20140264335A1
公开(公告)日：2014-09-18
申请号：US13845800
申请日：2013-03-18
Applicant: UNIMICRON TECHNOLOGY CORPORATION
Inventor： Dyi-Chung Hu , Tsung-Si Wang , Jui-Yang Ma
IPC: H01L21/66
CPC classification number: H01L22/14 , H01L22/32 , H01L24/48 , H01L2224/48227 , H01L2924/00014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads disposed in the testing region and electrically connected to the conductive pads, wherein the top surface area of each of the testing pads is greater than the top surface area of each of the conductive pads in order to facilitate a precise alignment of a probe with a corresponding one of the testing pads and prevent the probe from being blocked by the board body when in electrically testing an embedded circuit.
Abstract translation: 提供一种封装基板，包括具有布线区域和限定在其上的测试区域的板体，嵌入布线区域中的导电焊盘以及设置在测试区域中并电连接到导电焊盘的多个测试焊盘，其中， 每个测试焊盘的顶表面积大于每个导电焊盘的顶表面积，以便于探针与对应的一个测试焊盘的精确对准，并防止探针被板阻挡 身体在电测试嵌入式电路时。
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