公开(公告)号：US06656922B2

公开(公告)日：2003-12-02

申请号：US09845827

申请日：2001-04-30

Applicant: Youngro Byun ,  Yong-Kyu Lee

Inventor： Youngro Byun ,  Yong-Kyu Lee

IPC: A61K31727

CPC classification number: C08B37/00 ,  A61K31/727 ,  A61K47/542 ,  A61K47/554 ,  A61K47/61 ,  C08B37/0075

Abstract: Polysaccharides, which are widely used as an anticoagulation drugs, especially heparin, are clinically administered only by intravenous or subcutaneous injection because of their strong hydrophilicity and high negative charge. Amphiphilic heparin derivatives were synthesized by conjugation to bile acids, sterols, and alkanoic acids, respectively. These heparin derivatives were slightly hydrophobic, exhibited good solubility in water, and have high anticoagulation activity. These slightly hydrophobic heparin derivatives are efficiently absorbed in the gastrointestinal tract and can be used in oral dosage forms. Methods of using these amphiphilic heparin derivatives and similarly modified macromolecules for oral administration are also disclosed.

公开(公告)号：US06348378B1

公开(公告)日：2002-02-19

申请号：US09349728

申请日：1999-07-08

Applicant: Yong-Kyu Lee

Inventor： Yong-Kyu Lee

IPC: H01L21336

CPC classification number: H01L27/11543 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/66825

Abstract: A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region surrounding a drain region in the memory cell formation part, and surrounding drain and source regions of the low-voltage transistor formation part.

Abstract translation: 一种非易失性半导体器件及其制造方法，该器件具有存储单元形成部分和具有高电压和低电压晶体管形成部分的外围电路部分，其中该器件包括围绕漏极区域的反穿通区域 存储单元形成部分以及低压晶体管形成部分的周围的漏极和源极区域。

公开(公告)号：US20170053688A1

公开(公告)日：2017-02-23

申请号：US15153866

申请日：2016-05-13

Applicant: Bo-young SEO ,  Yong-seok CHUNG ,  Gwan-hyeob KOH ,  Yong-kyu LEE

Inventor： Bo-young SEO ,  Yong-seok CHUNG ,  Gwan-hyeob KOH ,  Yong-kyu LEE

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08

Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

Abstract translation: 电阻式存储装置包括具有多个存储单元的存储单元阵列和第一接地开关。 多个存储单元被布置成多行和多列，并且多个存储单元的第一列中的每个存储单元连接在第一位线和第一源极线之间。 第一接地开关与第一源极线并联连接，并且第一接地开关被配置为选择性地提供从第一位线到接地的第一电流路径，通过多个存储单元的第一列中的选定存储单元， 第一个源行，当前路径仅遍历第一个源行的一部分。

公开(公告)号：US20170047507A1

公开(公告)日：2017-02-16

申请号：US15093006

申请日：2016-04-07

Applicant: Bo-young SEO ,  Yong-kyu LEE

Inventor： Bo-young SEO ,  Yong-kyu LEE

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Abstract translation: 磁性随机存取存储器（MRAM）器件和半导体封装包括磁屏蔽层，其可以抑制由于外部磁场而引起的磁性取向误差和磁性隧道结（MTJ）结构的劣化中的至少一种。 半导体器件包括：包括MRAM的MRAM芯片; 以及包括上屏蔽层和通孔屏蔽层的磁屏蔽层。 上屏蔽层位于MRAM芯片的顶表面上，并且通孔屏蔽层从上屏蔽层延伸并通过MRAM芯片。

公开(公告)号：US09418739B2

公开(公告)日：2016-08-16

申请号：US14616806

申请日：2015-02-09

Applicant: Yong-Kyu Lee ,  Yeong-Taek Lee

Inventor： Yong-Kyu Lee ,  Yeong-Taek Lee

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72

Abstract: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

Abstract translation: 操作存储设备的方法包括： 对连接到所选择的存储单元的所选择的第一信号线施加第一组写入电压，向连接到未选择的存储器单元的未选择的第一信号线施加第一抑制电压，以及控制所选择的第二信号线的第一电压 连接到所选择的存储单元以小于第一设置写入电压，并且第一抑制电压和第一电压之间的差小于选择元件的阈值电压。

公开(公告)号：US20150287460A1

公开(公告)日：2015-10-08

申请号：US14616806

申请日：2015-02-09

Applicant: YONG-KYU LEE ,  YEONG-TAEK LEE

Inventor： YONG-KYU LEE ,  YEONG-TAEK LEE

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72

Abstract: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

Abstract translation: 操作存储器件的方法包括： 对连接到所选择的存储单元的所选择的第一信号线施加第一组写入电压，向连接到未选择的存储器单元的未选择的第一信号线施加第一抑制电压，以及控制所选择的第二信号线的第一电压 连接到所选择的存储单元以小于第一设置写入电压，并且第一抑制电压和第一电压之间的差小于选择元件的阈值电压。

公开(公告)号：US20150155024A1

公开(公告)日：2015-06-04

申请号：US14448717

申请日：2014-07-31

Applicant: Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

Inventor： Bo-Young SEO ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract translation: 磁存储器件包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。 磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。 还描述了相关系统和操作方法。

公开(公告)号：US08526231B2

公开(公告)日：2013-09-03

申请号：US13177873

申请日：2011-07-07

Applicant: Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

Inventor： Yong-Kyu Lee ,  Tea-Kwang Yu ,  Bo-Young Seo

IPC: G11C11/34

CPC classification number: G11C16/0408 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/3418

Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

Abstract translation: 非易失性存储器件包括第一扇区，包括第一扇区选择晶体管和连接到第一扇区选择晶体管的第一多个页，以及包括第二扇区选择晶体管的第二扇区和连接到第二扇区选择晶体管的第二多个页 扇区选择晶体管。 第一和第二多页中的每一页包括存储晶体管和选择晶体管，并且第一多页中的页数大于第二多页中的页数。

公开(公告)号：US20110038210A1

公开(公告)日：2011-02-17

申请号：US12912517

申请日：2010-10-26

Applicant: Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

Inventor： Yong-Kyu Lee ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Jung-Ho Moon ,  Soung-Youb Ha

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/26 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

Abstract translation: 在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。 第一电压被施加到存储晶体管的感测线。 大于第一电压的第二电压被施加到选择晶体管的字线。 将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。 可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

公开(公告)号：US07659573B2

公开(公告)日：2010-02-09

申请号：US11833019

申请日：2007-08-02

Applicant: Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

Inventor： Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

IPC: H01L29/76

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66651

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区，形成在凹陷区的内表面上的凹陷沟道，其形成在源区和漏区之间的半导体衬底上， 掺杂掺杂物的外延半导体膜。 半导体器件还包括形成在凹槽上的栅极绝缘膜，以及填充凹陷区并形成在栅极绝缘膜上的栅电极。