公开(公告)号：US20210250019A1

公开(公告)日：2021-08-12

申请号：US17245623

申请日：2021-04-30

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Vivekanandan Venugopal ,  Victor Zyuban

IPC: H03K3/037 ,  H03K3/356 ,  G11C19/18

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

公开(公告)号：US11005459B1

公开(公告)日：2021-05-11

申请号：US16391085

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Vivekanandan Venugopal ,  Victor Zyuban

IPC: H03K3/037 ,  G11C19/18 ,  H03K3/356

Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.

公开(公告)号：US10453505B2

公开(公告)日：2019-10-22

申请号：US15912449

申请日：2018-03-05

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Hemangi U. Gajjewar

IPC: G11C7/00 ,  G11C7/12 ,  G11C5/14 ,  G11C11/419

Abstract: An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.

公开(公告)号：US10217494B2

公开(公告)日：2019-02-26

申请号：US15635825

申请日：2017-06-28

Applicant: Apple Inc.

Inventor： Bharan Giridhar ,  Sachmanik Cheema ,  Greg M. Hess

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/12

Abstract: A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.

公开(公告)号：US09529533B1

公开(公告)日：2016-12-27

申请号：US15177596

申请日：2016-06-09

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Naveen Javarappa ,  Ajay Kumar Bhatia ,  Greg M. Hess

IPC: G11C5/14 ,  G06F3/06 ,  G06F1/32 ,  G06F1/26 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/418 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/172

Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.

Abstract translation: 公开了一种用于修改存储器阵列电源的电压电平的装置。 第一列可以包括耦合到第一本地电源信号的第一多个数据存储单元，并且第二列可以包括耦合到第二本地电源信号的第二多个数据存储单元。 第一开关可以被配置为根据第一选择信号的值将第一本地电源信号选择性地耦合到第一电源信号或第二电源信号，并且第二开关可被配置为选择性地将第二本地电源信号 根据第二选择信号的值将电源信号提供给第一电源信号或第二电源信号。

公开(公告)号：US20160071574A1

公开(公告)日：2016-03-10

申请号：US14482613

申请日：2014-09-10

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Ramesh Arvapalli ,  Andrew L. Arengo

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1078 ,  G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C11/413

Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Abstract translation: 公开了用于SRAM的低延迟初始化的方法和各种电路实施例。 在一个实施例中，IC包括耦合到至少一个功能电路块的SRAM。 SRAM包括以行和列排列的多个存储位置。 功能电路块和SRAM可以在不同的电源域中。 在初始上电或恢复电源时，功能电路块可以断言初始化信号以开始初始化过程。 响应于初始化信号，电平移位器可以在与SRAM相关联的解码器中强制断言各种选择/使能信号。 此后，可以将初始化数据写入SRAM。 可以逐行地执行写入初始化数据，其中一行中的所有列被基本上同时写入。

公开(公告)号：US20160062388A1

公开(公告)日：2016-03-03

申请号：US14935679

申请日：2015-11-09

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract translation: 公开了可以允许在时钟分配网络中检测周期和相位抖动的抖动检测电路的实施例。 抖动检测电路可以包括相位选择器，数据发生器，延迟链，逻辑电路和时钟存储元件。 相位选择器可以用于选择要用于发射时钟的时钟相位，并且数据发生器可以用于响应于发射时钟产生数据信号。 延迟链可以产生取决于数据信号的多个输出，并且时钟控制的存储元件可以用于从延迟链捕获多个输出，其可以通过逻辑电路与预期数据进行比较。

公开(公告)号：US20140177354A1

公开(公告)日：2014-06-26

申请号：US13725784

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Hitesh K. Gupta ,  Greg M. Hess ,  Naveen Javarappa

IPC: G11C7/00 ,  H03K19/00

CPC classification number: G11C7/00 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48 ,  H03K3/356121 ,  H03K3/356173 ,  H03K19/00

Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Abstract translation: 零保持器电路包括连接到源，输出和动态输入的动态输入PFET。 电路还包括连接到输出的时钟输入NFET，下拉节点和时钟输入。 电路还包括连接到下拉节点的动态输入NFET，参考电压和动态输入。 电路还包括反馈PFET和在源极和输出端之间串联连接的时钟输入PFET。 反馈PFET接收反馈信号，时钟输入PFET接收时钟输入。 电路还包括连接到输出端和节点的反馈NFET。 反馈NFET被配置为基于反馈信号将输出耦合到节点。 电路还包括被配置为基于输出和旁路输入提供反馈信号的或非门。

公开(公告)号：US20140177346A1

公开(公告)日：2014-06-26

申请号：US13725180

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Hitesh Gupta ,  Greg M. Hess ,  Aravind Kandala

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C8/10

Abstract: A memory array includes a number of word lines, with each word line coupled to a word line driver for memory write operations and a word line driver for memory read operations. A decode stage includes write logic for each word line and read logic for each word line. A word line driver stage includes a write word line driver and a read word line driver. The write logic for at least one world line is configured to enable the write word line driver for a memory write operation of the word line while prohibiting the read word line logic from enabling the read word line driver for a memory read operation of the word line.

Abstract translation: 存储器阵列包括多个字线，每个字线耦合到用于存储器写入操作的字线驱动器和用于存储器读取操作的字线驱动器。 解码级包括每个字线的写逻辑和每个字线的读逻辑。 字线驱动器级包括写字线驱动器和读字线驱动器。 用于至少一个世界线的写入逻辑被配置为使得写入字线驱动器能够进行字线的存储器写入操作，同时禁止读取字线逻辑使读取字线驱动器用于字线的存储器读取操作 。

公开(公告)号：US20140129884A1

公开(公告)日：2014-05-08

申请号：US13670739

申请日：2012-11-07

Applicant: APPLE INC.

Inventor： Greg M. Hess ,  James E. Burnette, II

IPC: G06F11/263

CPC classification number: G11C29/50012 ,  G11C8/16

Abstract: Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.

Abstract translation: 公开了寄存器文件测试电路的实施例，其可以允许在低电源电压下确定写入性能。 寄存器文件测试电路可以包括解码器，复用器，分频器和控制电路。 解码器可以用于选择寄存器文件中的寄存器单元，并且控制电路可操作以可控制地激活通过所选择的寄存器单元的读取和写入路径，从而允许将数据读取反向并重写回所选择的寄存器单元 寄存器单元格。