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23 条记录 (耗时 0.02 秒)

    Low noise low power charge pump system for phase lock loop
    11.
    发明授权
    Low noise low power charge pump system for phase lock loop 有权
    用于锁相环的低噪声低功率电荷泵系统

    公开(公告)号：US06215363B1

    公开(公告)日：2001-04-10

    申请号：US09405752

    申请日：1999-09-27

    申请人： Matteo Conta ,  Akbar Ali

    发明人： Matteo Conta ,  Akbar Ali

    IPC分类号： H03L7089

    CPC分类号： H03L7/081 ,  H03L7/0802 ,  H03L7/0895 ,  H03L7/18

    摘要： In a phase lock loop, a charge pump includes a current mirror circuit. The current mirror circuit contains a bias current source and a current mirror source which mirrors the current of the bias current source. The current mirror source is turned on and off in accordance with an output signal from a phase detector to produce correction signals for a VCO. To conserve power, circuits are provided for turning the bias current source on just before it is needed by the current mirror source and for turning the bias current source off just after the current mirror source turns off.

    摘要翻译： 在锁相环中，电荷泵包括电流镜电路。 电流镜电路包含偏置电流源和反映偏置电流源的电流的电流镜源。 电流镜源根据来自相位检测器的输出信号导通和截止，以产生用于VCO的校正信号。 为了节省电力，提供电路用于在电流镜源需要之前转动偏置电流源，并且在电流镜源关闭之后关闭偏置电流源。

    Gated delay-locked loop for clock generation applications
    12.
    发明授权
    Gated delay-locked loop for clock generation applications 有权
    用于时钟发生应用的门控延迟锁定环

    公开(公告)号：US06208183B1

    公开(公告)日：2001-03-27

    申请号：US09302755

    申请日：1999-04-30

    申请人： Larry B. Li ,  Akbar Ali ,  Matteo Conta

    发明人： Larry B. Li ,  Akbar Ali ,  Matteo Conta

    IPC分类号： H03L700

    CPC分类号： H03L7/081 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/183

    摘要： A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

    摘要翻译： 门控延迟锁定环，其产生与参考时钟的频率的整数倍的频率相位并且具有频率的输出时钟。 门控延迟锁定环路包括具有第一和第二串联连接的电压控制延迟元件的电压控制选通振荡器，每个引入时间延迟以产生第一延迟时钟和输出时钟。 S-R触发器在其R输入端接收第一个延迟时钟，并在其S输入端接收输出时钟或参考时钟，以产生一个回路时钟。 环路时钟被提供给第一延迟元件。 多路复用器每N个周期选择参考时钟作为触发器的S输入，并选择输出时钟作为S输入剩余的N-1个周期。 相位检测器，电荷泵和环路滤波器将输出时钟的相位与参考时钟的相位进行比较，并向延迟元件施加电压以校正任何相位差。

    Effectively differential, multiple input OR/NOR gate architecture
    13.
    发明授权
    Effectively differential, multiple input OR/NOR gate architecture 失效
    有效差分，多输入OR / NOR门架构

    公开(公告)号：US5945848A

    公开(公告)日：1999-08-31

    申请号：US752016

    申请日：1996-11-19

    申请人： Akbar Ali

    发明人： Akbar Ali

    IPC分类号： H03K19/086

    CPC分类号： H03K19/086

    摘要： A multiple input, low voltage, OR/NOR gate architecture based on a single-ended OR/NOR gate circuit, wherein a plurality of input transistors are connected in parallel. A reference transistor connects to the input transistors. A feedback means connects the NOR output signal to the base or gate of the reference transistor. The feedback means provides an effectively differential input for the multiple input circuit, without increasing circuit complexity, thereby providing enhanced noise margin characteristics.

    摘要翻译： 基于单端OR / NOR门电路的多输入，低电压，或/或门门结构，其中多个输入晶体管并联连接。 参考晶体管连接到输入晶体管。 反馈装置将NOR输出信号连接到参考晶体管的基极或栅极。 反馈装置为多输入电路提供有效的差分输入，而不增加电路复杂度，从而提供增强的噪声容限特性。

    Frequency prescaler
    15.
    发明授权
    Frequency prescaler 有权
    频率预分频器

    公开(公告)号：US06968029B1

    公开(公告)日：2005-11-22

    申请号：US10910731

    申请日：2004-08-03

    申请人： Chang-Hyeon Lee ,  Akbar Ali

    发明人： Chang-Hyeon Lee ,  Akbar Ali

    IPC分类号： H03K21/00 ,  H03K23/48

    CPC分类号： H03K23/483

    摘要： A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but may have a dead-zone period where it may fail to respond to a generated mode command. The dual modulus prescaler also has an output line that is synchronized to an extender section. The extender section is used to further divide the input signal, and is synchronized to an adjustable counter section. A sync controller circuit receives an output from the counter section, as well as a timing signal from the extender, and generates the mode signal on the mode command line. In this arrangement, the sync controller generates the mode signal at a time when the low order dual modulus is in a condition to change divide modes, thereby avoiding providing the signal during the dead-zone period.

    摘要翻译： 提供了一种同步预分频器，其具有用于接收与低阶双模预分频器同步的输入信号的输入线。 双模预分频器通常根据模式命令行分隔，但可能具有死区周期，其中它可能无法响应生成的模式命令。 双模预分频器还具有与扩展器部分同步的输出线。 扩展器部分用于进一步分割输入信号，并与可调节的计数器部分同步。 同步控制器电路接收来自计数器部分的输出以及来自延长器的定时信号，并在模式命令行上生成模式信号。 在这种布置中，同步控制器在低阶双模量处于改变分频模式的条件下产生模式信号，从而避免在死区期间提供信号。

    Charge pump having reduced switching noise
    16.
    发明授权
    Charge pump having reduced switching noise 有权
    电荷泵具有降低的开关噪声

    公开(公告)号：US06954090B2

    公开(公告)日：2005-10-11

    申请号：US10601959

    申请日：2003-06-23

    申请人： Chang-Hyeon Lee ,  Akbar Ali

    发明人： Chang-Hyeon Lee ,  Akbar Ali

    IPC分类号： H03L7/08 ,  H03L7/089 ,  H03L7/06

    CPC分类号： H03L7/0802 ,  H03L7/0895 ,  H03L7/0896

    摘要： A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.

    摘要翻译： 提供了一种具有能够与开关晶体管隔离开关噪声的互补晶体管的低功率电荷泵。 电荷泵使用在幅度和时间上匹配的充电电流来降低电荷泵输出中的开关噪声。 电荷泵也设计用于锁相环。

    Fully integrated broadband RF voltage amplifier with enhanced voltage gain and method
    17.
    发明授权
    Fully integrated broadband RF voltage amplifier with enhanced voltage gain and method 有权
    完全集成的宽带射频电压放大器，具有增强的电压增益和方法

    公开(公告)号：US06265944B1

    公开(公告)日：2001-07-24

    申请号：US09405766

    申请日：1999-09-27

    申请人： Matteo Conta ,  Akbar Ali

    发明人： Matteo Conta ,  Akbar Ali

    IPC分类号： H03F345

    CPC分类号： H03F3/45188 ,  H03F2203/45544 ,  H03F2203/45554 ,  H03F2203/45594 ,  H03F2203/45631 ,  H03F2203/45702

    摘要： RF voltage amplifier circuits which have high voltage amplifier gain and input signal frequency range, and a method for boosting the voltage amplifier gain and input signal frequency range in such circuits is provided. A method includes the steps of providing a voltage amplifier having a transistor with the grounded source and the drain connected to a power supply via a resistive load, and providing an integrated inductor for biasing the transistor, having an inductor connecting an input signal terminal to the gate of the transistor and a capacitor connecting the gate and the source of the transistor. The next step includes selecting a resonant frequency of the integrated inductor at a frequency where the voltage amplifier gain is starting to roll-off, for boosting the voltage amplifier gain and the input signal frequency range. The integrated inductor preferably operates at a resonant frequency approximately matching the roll-off frequency of the voltage amplifier. In another embodiment the voltage amplifier has a common emitter (CE) gain stage, a common base (CB) cascade stage directly-coupled to the CE gain stage, and a constant current mirror source. The integrated inductor has two inductors, each connected to one input of the amplifier input signal pair and a capacitor connecting the inductors. This circuit can be adapted for fully differential operation mode or for single ended operation mode.

    摘要翻译： 提供具有高电压放大器增益和输入信号频率范围的RF电压放大器电路，以及用于升高这些电路中的电压放大器增益和输入信号频率范围的方法。 一种方法包括以下步骤：提供具有晶体管的电压放大器，其中接地源极和漏极经由电阻性负载连接到电源，并且提供用于偏置晶体管的集成电感器，其具有将输入信号端子连接到 晶体管的栅极和连接晶体管的栅极和源极的电容器。 下一步包括以电压放大器增益开始滚降的频率选择集成电感器的谐振频率，以升高电压放大器增益和输入信号频率范围。 集成电感器优选以大致匹配电压放大器的滚降频率的谐振频率工作。 在另一个实施例中，电压放大器具有公共发射极（CE）增益级，直接连接到CE增益级的公共基极（CB）级联级和恒定电流镜源。 集成电感器具有两个电感器，每个电感器连接到放大器输入信号对的一个输入端和连接电感器的电容器。 该电路可适用于全差分运行模式或单端运行模式。