公开(公告)号：US09459234B2

公开(公告)日：2016-10-04

申请号：US13480161

申请日：2012-05-24

申请人： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

发明人： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

IPC分类号： H01L51/05 ,  G01N27/414 ,  H01L51/00

CPC分类号： G01N27/4145 ,  G01N27/414 ,  G01N27/4148 ,  H01L21/84 ,  H01L27/1203 ,  H01L51/0093

摘要： The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

摘要翻译： 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET器件可以包括衬底; 设置在基板的第一表面上的栅极结构和形成在基板的第二表面上的界面层。 界面层可以允许将受体置于界面层上以检测生物分子或生物实体的存在。

公开(公告)号：US08723123B2

公开(公告)日：2014-05-13

申请号：US13595743

申请日：2012-08-27

申请人： Alexander Kalnitsky ,  Chia-Hua Chu ,  Fei-Lung Lai ,  Chun-Wen Cheng ,  Chun-Ren Cheng ,  Yi-Hsien Chang

发明人： Alexander Kalnitsky ,  Chia-Hua Chu ,  Fei-Lung Lai ,  Chun-Wen Cheng ,  Chun-Ren Cheng ,  Yi-Hsien Chang

IPC分类号： G01J5/20

CPC分类号： G01J1/1626 ,  G01J1/4204 ,  G01J3/465 ,  H01L31/02164 ,  H01L31/103 ,  H01L31/105

摘要： A light detector includes a first light sensor and a second light sensor to detect incident light. A Ge film is disposed over the first light sensor to pass infra-red (IR) wavelength light and to block visible wavelength light. The Ge film does not cover the second light sensor.

摘要翻译： 光检测器包括第一光传感器和用于检测入射光的第二光传感器。 将Ge膜设置在第一光传感器上以通过红外（IR）波长的光并阻挡可见波长的光。 Ge膜不覆盖第二个光传感器。

公开(公告)号：US08101511B2

公开(公告)日：2012-01-24

申请号：US12774762

申请日：2010-05-06

申请人： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

发明人： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7833

摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。

公开(公告)号：US20110176368A1

公开(公告)日：2011-07-21

申请号：US13077065

申请日：2011-03-31

申请人： Alexander Kalnitsky ,  Michael Church

发明人： Alexander Kalnitsky ,  Michael Church

IPC分类号： G11C16/04 ,  H01L29/94

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

摘要翻译： 根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。 浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。 高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的扩展漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。 浮置栅极PMOS晶体管可以存储逻辑状态。 可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

公开(公告)号：US07903465B2

公开(公告)日：2011-03-08

申请号：US11861111

申请日：2007-09-25

申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/0433

摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

公开(公告)号：US07700977B2

公开(公告)日：2010-04-20

申请号：US12037569

申请日：2008-02-26

申请人： Michael David Church ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

发明人： Michael David Church ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L27/0814

摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

摘要翻译： 集成电路包括并联连接的第一和第二二极管。 第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。 第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠 并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。

公开(公告)号：US20080135968A1

公开(公告)日：2008-06-12

申请号：US11621443

申请日：2007-01-09

申请人： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

发明人： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

IPC分类号： H01L31/02

CPC分类号： H01L31/103 ,  H01L27/1443 ,  H01L31/02162

摘要： Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.

摘要翻译： 本发明的实施例涉及在抑制红外光的同时主要响应于可见光的光传感器。 这种传感器作为环境光传感器是特别有用的，因为这样的传感器可用于提供类似于人眼的光谱响应。 本发明的实施例还涉及提供这种光传感器的方法，以及使用这种光传感器的方法。

公开(公告)号：US20070247915A1

公开(公告)日：2007-10-25

申请号：US11498672

申请日：2006-08-02

申请人： Alexander Kalnitsky ,  Michael Church

发明人： Alexander Kalnitsky ,  Michael Church

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

公开(公告)号：US06855585B1

公开(公告)日：2005-02-15

申请号：US10002429

申请日：2001-10-31

申请人： Alexander Kalnitsky ,  Joseph Paul Elull ,  Ralph Wall ,  Robert F. Scheer ,  Jonathan Herman ,  Glenn Nobinger ,  Viktor Zekeriya

发明人： Alexander Kalnitsky ,  Joseph Paul Elull ,  Ralph Wall ,  Robert F. Scheer ,  Jonathan Herman ,  Glenn Nobinger ,  Viktor Zekeriya

IPC分类号： H01L27/01 ,  H01L27/08 ,  H01L21/302

CPC分类号： H01L27/0802 ,  H01L27/016

摘要： A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.

摘要翻译： 一种在衬底上形成多个电阻器的方法。 该方法最初包括在衬底上提供第一电阻器。 在第一电阻器上沉积，图案化和选择性蚀刻第一电介质层。 第二电阻材料设置在第一介电层上。 此外，着陆垫材料设置在第二电阻材料上。 然后选择性地蚀刻着陆焊盘材料和第二电阻材料。 选择性蚀刻在第一区域中形成用于第一电阻器的触点，并且在第二区域中形成第二电阻器和相关联的触点。

公开(公告)号：US06686250B1

公开(公告)日：2004-02-03

申请号：US10300105

申请日：2002-11-20

申请人： Alexander Kalnitsky ,  Michael Rowlandson ,  Fanling H. Yang ,  Sang Park ,  Robert F. Scheer

发明人： Alexander Kalnitsky ,  Michael Rowlandson ,  Fanling H. Yang ,  Sang Park ,  Robert F. Scheer

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L29/66242

摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

摘要翻译： 提供自对准双极晶体管及其形成方法。 双极晶体管具有由双层多晶硅形成的由y形结构表征的发射极区域。 双层多晶硅包括第一多晶硅发射极结构和第二多晶硅发射极结构。 形成双极晶体管的方法包括在衬底上形成发射极叠层。 发射极堆叠包括第一多晶硅发射极结构和插塞结构。 发射极堆叠将衬底限定为掩模部分并暴露于相邻部分。 暴露的相邻部分被选择性掺杂掺杂剂以限定非本征基区，其中掺杂剂被阻止进入掩蔽部分。 在选择性地掺杂非本征基极区域之后，将插塞结构从发射极堆叠移除，并且第二多晶硅发射极结构形成在第一多晶硅发射极结构上以限定双极晶体管的发射极区域。