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11.发明公开公开(公告)号：US20240243012A1
公开(公告)日：2024-07-18
申请号：US18622588
申请日：2024-03-29
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L22/20 , H01L24/32 , H01L24/73 , H01L25/03 , H01L25/16 , H01L25/18 , H01L24/17 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2224/24195 , H01L2924/12 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104
Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.
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12.发明公开公开(公告)号：US20230335440A1
公开(公告)日：2023-10-19
申请号：US18307554
申请日：2023-04-26
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L25/16 , H01L25/03 , H01L25/18 , H01L22/20 , H01L24/32 , H01L24/73 , H01L24/17 , H01L2924/1427 , H01L2924/1436 , H01L2924/19042 , H01L2924/1432 , H01L2924/19103 , H01L2224/12105 , H01L2224/1703 , H01L2924/19104 , H01L2224/16265 , H01L2924/15192 , H01L2224/16235 , H01L2924/19041 , H01L2224/16227 , H01L2224/24195 , H01L2924/1433 , H01L2924/18162 , H01L2224/1403 , H01L2224/16145 , H01L2924/15311 , H01L2924/18161 , H01L2224/17181 , H01L2924/12 , H01L2924/1205 , H01L2924/1206
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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13.发明授权公开(公告)号：US11670548B2
公开(公告)日：2023-06-06
申请号：US17080609
申请日：2020-10-26
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L22/20 , H01L24/32 , H01L24/73 , H01L25/03 , H01L25/16 , H01L25/18 , H01L24/17 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2224/24195 , H01L2924/12 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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公开(公告)号：US09236355B2
公开(公告)日：2016-01-12
申请号：US14331363
申请日：2014-07-15
Applicant: Apple Inc.
Inventor： Jun Zhai , Mengzhi Pang , Se Young Yang , Leland W. Lew
IPC: H01L23/60 , H01L23/538 , H01L23/485 , H01L23/552 , H01L25/00 , H01L25/065 , H01L25/18 , H01L23/00 , H01L23/367
CPC classification number: H01L23/552 , H01L21/561 , H01L23/3128 , H01L23/367 , H01L23/3675 , H01L23/49805 , H01L23/49811 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/16145 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2224/73257 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06589 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/01029 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2224/81
Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.
Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 第一衬底可以包括电连接组件的第一组电导体。 在一些实施例中，组件可以包括耦合到第一衬底的至少一个电导体，使得电导体中的至少一个暴露于半导体器件封装组件的周边表面。 在一些实施例中，组件可以包括使用第二组电导体电连接到第一衬底的第二表面的第一裸片。 组件可以包括耦合到第一管芯的电子存储器模块。 在一些实施例中，组件可以包括施加到组件的上表面并且电耦合到暴露的电导体中的至少一个的屏蔽。 在使用过程中，屏蔽可能会阻碍电磁干扰。
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15.发明申请PACKAGE WITH MEMORY DIE AND LOGIC DIE INTERCONNECTED IN A FACE-TO-FACE CONFIGURATION 审中-公开在面对面配置中互连的存储器和逻辑模块的封装公开(公告)号：US20150380392A1
公开(公告)日：2015-12-31
申请号：US14317799
申请日：2014-06-27
Applicant: Apple Inc.
Inventor： Mengzhi Pang , Jun Zhai
CPC classification number: H01L25/18 , H01L21/56 , H01L21/568 , H01L23/50 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/13124 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/24195 , H01L2224/73209 , H01L2224/81005 , H01L2224/92124 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/1431 , H01L2924/1434 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2224/81
Abstract: A semiconductor device package includes a logic die coupled to a memory die in a face-to-face configuration with small interconnect pitch (at most about 50 μm) and small distances between the die (at most about 50 μm). The logic die may be connected to a redistribution layer with terminals that are fanned out, or spaced out, to provide space for the face-to-face connections to the memory die. The memory die may be connected to the logic die before or after the logic die is connected to the redistribution layer. The logic die and the memory die may be at least partially encapsulated in an encapsulant. Routing in the redistribution layer may connect the logic die and/or the memory die to ball grid array terminals coupled to the bottom of the redistribution layer and/or discrete devices coupled to the redistribution layer.
Abstract translation: 半导体器件封装包括以小的互连间距（至多约50μm）和管芯之间的距离（至多约50μm）以面对面配置耦合到存储器管芯的逻辑管芯。 逻辑管芯可以连接到再分配层，其中端子被扇形出或间隔开，以提供用于与存储管芯的面对面连接的空间。 在逻辑管芯连接到再分配层之前或之后，存储器管芯可以连接到逻辑管芯。 逻辑管芯和存储器管芯可以至少部分地封装在密封剂中。 再分配层中的路由可以将逻辑管芯和/或存储器管芯连接到耦合到再分配层的底部的耦合到再分配层的离散器件的球栅阵列终端。
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Patent Agency Ranking
公开(公告)号：US20150171063A1
公开(公告)日：2015-06-18
申请号：US14192145
申请日：2014-02-27
Applicant: Apple Inc.
Inventor： Jun Zhai , Yizhang Yang , Mengzhi Pang
IPC: H01L25/16 , H01L23/538 , H01L23/00 , H01L23/367 , H01L25/00
CPC classification number: H01L25/165 , H01L23/36 , H01L23/49816 , H01L23/5384 , H01L23/5389 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/08225 , H01L2224/16145 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2224/73257 , H01L2224/81894 , H01L2224/83894 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06589 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/20643 , H01L2924/20644 , H01L2924/20645 , H01L2924/20646 , H01L2924/20647 , H01L2924/20648 , H01L2924/20649
Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die electrically connected to the first substrate such that the first die is directly bonded to the first substrate. The semiconductor device package assembly may include a second substrate directly bonded to a surface of the first die. The semiconductor device package assembly may include an electronic memory module. The electronic memory module may be directly bonded to the second substrate. The semiconductor device package assembly may include a thermally conductive material directly applied to the electronic memory module. The semiconductor device package assembly may include a heat spreader directly bonded to the thermally conductive material. The heat spreader may function to transfer heat from the first die and the electronic memory module through the heat spreader from the first side to the second side.
Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 半导体器件封装组件可以包括电连接到第一衬底的第一裸片，使得第一裸片直接结合到第一衬底。 半导体器件封装组件可以包括直接接合到第一管芯的表面的第二衬底。 半导体器件封装组件可以包括电子存储器模块。 电子存储器模块可以直接结合到第二衬底。 半导体器件封装组件可以包括直接施加到电子存储器模块的导热材料。 半导体器件封装组件可以包括直接结合到导热材料的散热器。 散热器可以起到将热量从第一模具和电子存储器模块通过散热器从第一侧传递到第二侧的功能。
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17.发明授权公开(公告)号：US11967528B2
公开(公告)日：2024-04-23
申请号：US18307554
申请日：2023-04-26
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L22/20 , H01L24/32 , H01L24/73 , H01L25/03 , H01L25/16 , H01L25/18 , H01L24/17 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2224/24195 , H01L2924/12 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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公开(公告)号：US11069665B2
公开(公告)日：2021-07-20
申请号：US16205679
申请日：2018-11-30
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Chonghua Zhong , Jun Zhai , Long Huang , Mengzhi Pang , Rohan U. Mandrekar
IPC: H01L25/16 , G01R31/64 , H01L23/525 , H01L21/66 , H01L49/02
Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.
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19.发明申请公开(公告)号：US20210043511A1
公开(公告)日：2021-02-11
申请号：US17080609
申请日：2020-10-26
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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20.发明授权公开(公告)号：US09935076B1
公开(公告)日：2018-04-03
申请号：US15264087
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
CPC classification number: H01L21/77 , H01L24/17 , H01L25/03 , H01L25/16 , H01L25/18 , H01L2224/12105 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2224/24195 , H01L2924/1427 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104
Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
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