公开(公告)号：US20130089952A1

公开(公告)日：2013-04-11

申请号：US13270890

申请日：2011-10-11

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Chung-Shi Liu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Chung-Shi Liu

IPC: H01L21/60 ,  H01L23/12 ,  H01L21/603

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75754 ,  H01L2224/7698 ,  H01L2224/81001 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83102 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/013

Abstract: Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.

Abstract translation: 公开了用于半导体器件的封装处理工具和封装方法。 在一个实施例中，用于半导体器件的封装处理工具包括包括框架的机械结构。 框架包括适于将多个集成电路管芯保持在其中的多个孔。 框架包括至少一个中空区域。

公开(公告)号：US20120267423A1

公开(公告)日：2012-10-25

申请号：US13089977

申请日：2011-04-19

Applicant: Kuei-Wei Huang ,  Wei-Hung Lin ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Bor-Ping Jang ,  Chung-Shi Liu

Inventor： Kuei-Wei Huang ,  Wei-Hung Lin ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Bor-Ping Jang ,  Chung-Shi Liu

IPC: B23K1/20 ,  B25J15/06

CPC classification number: H01L21/6838 ,  H01L24/75

Abstract: A vacuum tip and methods for processing thin integrated circuit dies. A vacuum tip for attaching to an integrated circuit die is disclosed comprising a vacuum port configured to connect to a vacuum supply on an upper surface and having a bottom surface; and at least one vacuum hole extending through the vacuum tip and exposed at the bottom surface of the vacuum tip; wherein the vacuum tip is configured to physically contact a surface of an integrated circuit die. Methods for processing integrated circuit dies are disclosed.

Abstract translation: 真空尖端和薄集成电路管芯的处理方法。 公开了一种用于连接到集成电路管芯的真空端头，其包括被构造成连接到上表面上的具有底表面的真空源的真空端口; 以及至少一个真空孔，其延伸穿过真空尖端并暴露在真空尖端的底表面处; 其中所述真空尖端被配置为物理地接触集成电路管芯的表面。 公开了集成电路管芯的处理方法。

公开(公告)号：USD586933S1

公开(公告)日：2009-02-17

申请号：US29250336

申请日：2006-11-10

Applicant: Chun-Cheng Lin

Designer： Chun-Cheng Lin

公开(公告)号：US20090032822A1

公开(公告)日：2009-02-05

申请号：US11939552

申请日：2007-11-13

Applicant: Chun-Cheng Lin ,  Abram Chang ,  Sheng-Jia Sheu ,  Eddie Huang

Inventor： Chun-Cheng Lin ,  Abram Chang ,  Sheng-Jia Sheu ,  Eddie Huang

IPC: H01L33/00

CPC classification number: H05K1/0203 ,  H01L33/647 ,  H05K1/18 ,  H05K2201/10106 ,  H05K2201/10659

Abstract: A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin.

Abstract translation: 大功率发光二极管，大功率发光二极管包括发光二极管芯片，主模块，两个第一电极引脚，两个第二电极引脚和至少一个散热板。 主模块具有凹面，发光二极管芯片位于凹面。 第一电极引脚连接到主模块的第一侧，并且电连接到发光二极管芯片。 第二电极引脚布置在主模块的相对于第一电极引脚的第二侧，其中第二电极引脚和第一电极引脚电气相对。 第二电极引脚电连接到发光二极管芯片。 散热板与主模块的一部分连接在第一电极销和第二电极销之间。

公开(公告)号：US20080117622A1

公开(公告)日：2008-05-22

申请号：US11600094

申请日：2006-11-16

Applicant: Chun-Cheng Lin

Inventor： Chun-Cheng Lin

IPC: F21V33/00 ,  A47J37/07

CPC classification number: F21L4/04 ,  A47J37/0786 ,  F21V17/007 ,  F21V21/0965 ,  F21V33/008

Abstract: A lighting device for a barbecue stove includes a fixing seat mounted on a faceplate of the barbecue stove, a lamp body detachably mounted on the fixing seat, a lighting member mounted on a first end of the lamp body, a drive member mounted on a second end of the lamp body to drive the lamp body, and a magnetic member mounted on the drive member. Thus, the magnetic member of the lighting device is magnetically attached to a metallic surface located at any position of the barbecue stove so that the lighting device is arbitrarily attached to any position of the barbecue stove to provide a lighting effect.

Abstract translation: 一种用于烧烤炉的照明装置包括安装在烧烤炉的面板上的固定座，可拆卸地安装在固定座上的灯体，安装在灯体的第一端上的照明件，安装在第二个 灯体的端部以驱动灯体，以及安装在驱动构件上的磁性构件。 因此，照明装置的磁性构件被磁性地附接到位于烧烤炉的任何位置的金属表面，使得照明装置任意地附接到烧烤炉的任何位置以提供照明效果。

公开(公告)号：US20050046204A1

公开(公告)日：2005-03-03

申请号：US10653267

申请日：2003-09-03

Applicant: Chun-Cheng Lin

Inventor： Chun-Cheng Lin

IPC: E05B1/00 ,  E05B3/00 ,  E05B55/00

CPC classification number: E05B3/003 ,  E05B1/0007 ,  E05B55/005 ,  Y10T292/93

Abstract: A latching axle assembly includes an axle having a head formed at an end of the axle. Multiple recesses are defined at an outer periphery of the head. A cap has multiple protrusions formed at an inner wall of the cap and respectively positioned in the recesses to detachably mount the cap on the head. The cap can be easily and quickly mounted on the axle, and can be detached from an axle found to be defective.

Abstract translation: 锁定轴组件包括具有在轴的端部处形成的头部的车轴。 多个凹口限定在头部的外周。 帽在盖的内壁处形成有多个突出部，并且分别定位在凹部中以将帽可拆卸地安装在头部上。 盖可以方便快捷地安装在轴上，并且可以从发现有缺陷的轴上拆下。

公开(公告)号：US09412717B2

公开(公告)日：2016-08-09

申请号：US13289719

申请日：2011-11-04

Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00 ,  B29C43/18 ,  H01L21/56 ,  B29C33/68

CPC classification number: H01L24/97 ,  B29C33/68 ,  B29C43/18 ,  H01L21/563 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/00

Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.

Abstract translation: 用于成型模制底部填料的方法和装置。 公开了一种方法，其包括在第一温度下将倒装芯片衬底加载到模压机的上模追逐和下模追逐中的所选择的一个中; 将模制的底部填充材料定位在上模具和下模具中的至少一个中，同时保持低于模制的底部填充材料的熔融温度的第一温度; 形成密封的模腔并在模腔中产生真空; 将模制的底部填充材料的温度提高到大于熔点的第二温度，以使模制的底部填充材料在形成底部填充层的倒装芯片衬底上流动并形成包覆成型层; 并将所述倒装芯片基板冷却至基本上低于所述模制底部填充材料的熔融温度的第三温度。 公开了一种装置。

公开(公告)号：US09233307B2

公开(公告)日：2016-01-12

申请号：US13588166

申请日：2012-08-17

Applicant: Hsing-Yuan Shen ,  Chun-Cheng Lin

Inventor： Hsing-Yuan Shen ,  Chun-Cheng Lin

IPC: G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  A63F13/22 ,  G06F3/038

CPC classification number: A63F13/22 ,  G06F3/038

Abstract: A fully automatic simulation system for an input device permits storage in advance of executable applications and associated simulation setting flies into a database, and then combination of the detection, automatic data searching and matching, transmission and conversion, enabling rapid and convenient operation by the users, whenever they operate various applications or whether they adopt a keyboard, mouse or joystick as the simulation controller.

Abstract translation: 用于输入设备的全自动仿真系统允许在可执行应用程序之前进行存储，并将相关的仿真设置进入数据库，然后组合检测，自动数据搜索和匹配，传输和转换，使用户能够快速方便地进行操作 ，每当他们操作各种应用程序，或者他们是否采用键盘，鼠标或操纵杆作为模拟控制器。

公开(公告)号：US08895497B2

公开(公告)日：2014-11-25

申请号：US12960805

申请日：2010-12-06

Applicant: Chun-Cheng Lin ,  Wun-Shaing Wayne Chang ,  Biing-Jiun Uang ,  Jang-Yang Chang ,  Jo-Chun Chen ,  Hsing-Pang Hsieh

Inventor： Chun-Cheng Lin ,  Wun-Shaing Wayne Chang ,  Biing-Jiun Uang ,  Jang-Yang Chang ,  Jo-Chun Chen ,  Hsing-Pang Hsieh

IPC: C07D295/215 ,  C07D307/68

CPC classification number: C07C261/04 ,  C07C237/22 ,  C07C2601/02 ,  C07C2601/04 ,  C07C2601/14 ,  C07C2601/18 ,  C07C2603/18 ,  C07D209/42 ,  C07D217/26 ,  C07D241/24 ,  C07D249/18 ,  C07D295/215 ,  C07D307/68 ,  C07D309/32 ,  C07D319/18 ,  C07D333/24

Abstract: Cathepsin S inhibitors having formula (I), (II), (III) or (IV) as shown in the specification. These inhibitors can be used to treat cancer and autoimmune/inflammatory diseases.

Abstract translation: 具有式（I），（II），（III）或（IV）的组织蛋白酶S抑制剂，如说明书所示。 这些抑制剂可用于治疗癌症和自身免疫/炎性疾病。

公开(公告)号：US08884431B2

公开(公告)日：2014-11-11

申请号：US13228768

申请日：2011-09-09

Applicant: Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

Inventor： Chih-Wei Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Hsiu-Jen Lin ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Kuei-Wei Huang ,  Wei-Hung Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/683 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/03 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/52 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06515 ,  H01L2224/09181 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.

Abstract translation: 公开了用于半导体器件的封装方法和结构。 在一个实施例中，封装的半导体器件包括具有第一表面和与第一表面相对的第二表面的再分配层（RDL）。 至少一个集成电路耦合到RDL的第一表面，并且多个金属凸块耦合到RDL的第二表面。 模制化合物设置在RDL的至少一个集成电路和第一表面上。