公开(公告)号：US12149024B2

公开(公告)日：2024-11-19

申请号：US17853861

申请日：2022-06-29

Applicant: Chun-Cheng Lin ,  Shy-Luen Chern ,  Chih-Hsiang Tang ,  Hong-Wen Lee

Inventor： Chun-Cheng Lin ,  Shy-Luen Chern ,  Chih-Hsiang Tang ,  Hong-Wen Lee

IPC: H01R13/62 ,  H01R13/17 ,  H01R13/24 ,  H01R13/502 ,  H01R13/629

Abstract: An electrical connector assembly including a first connector and a second connector to be mated with each other is provided. The first connector includes a first body, and at least one first terminal and multiple second terminals disposed therein. The second terminals are symmetrically arranged at opposite sides of the first terminal. The second connector includes a second body, at least one third terminal movably disposed in the second body, multiple fourth terminals disposed in the second body and symmetrically arranged at opposite sides of the third terminal, and a driving module electrically connected to at least one of the fourth terminals and structurally connected to the third terminal. In the mating process of the first and second connector, the second terminals and the fourth terminals are electrically connected firstly, to trigger the driving module to move the third terminal to be structurally and electrically connected to the first terminal.

公开(公告)号：US10522452B2

公开(公告)日：2019-12-31

申请号：US13276143

申请日：2011-10-18

Applicant: Kuei-Wei Huang ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng ,  Ching-Shi Liu

Inventor： Kuei-Wei Huang ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng ,  Ching-Shi Liu

IPC: H01L21/00 ,  H01L23/498

Abstract: Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

公开(公告)号：US09030022B2

公开(公告)日：2015-05-12

申请号：US13280157

申请日：2011-10-24

Applicant: Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/31105 ,  H01L21/565 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

Abstract translation: 一种器件包括在顶表面上具有导电特征的封装元件和模塑在第一封装元件的顶表面上的聚合物区域。 多个开口从聚合物区域的顶表面延伸到聚合物区域中，其中每个导电特征通过多个开口中的一个露出。 多个开口包括具有第一水平尺寸的第一开口和具有不同于第一水平尺寸的第二水平尺寸的第二开口。

公开(公告)号：US08664040B2

公开(公告)日：2014-03-04

申请号：US13331061

申请日：2011-12-20

Applicant: Chen-Hua Yu ,  Chung-Shi Liu ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/31 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/14 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.

Abstract translation: 一种方法包括对包装进行蚀刻步骤。 该包装包括包装部件，在包装部件的顶表面上的连接器，结合到包装部件的顶表面的管芯，以及模制在包装部件的顶表面上的模制材料。 成型材料覆盖连接器，其中通过蚀刻步骤去除覆盖连接器的成型材料的一部分，并且连接器被暴露。

公开(公告)号：US20130115735A1

公开(公告)日：2013-05-09

申请号：US13289719

申请日：2011-11-04

Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chun-Cheng Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/98 ,  B29C35/08

CPC classification number: H01L24/97 ,  B29C33/68 ,  B29C43/18 ,  H01L21/563 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/00

Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.

Abstract translation: 用于成型模制底部填料的方法和装置。 公开了一种方法，其包括在第一温度下将倒装芯片衬底加载到模压机的上模追逐和下模追逐中的所选择的一个中; 将模制的底部填充材料定位在上模具和下模具中的至少一个中，同时保持低于模制的底部填充材料的熔融温度的第一温度; 形成密封的模腔并在模腔中产生真空; 将模制的底部填充材料的温度提高到大于熔点的第二温度，以使模制的底部填充材料在形成底部填充层的倒装芯片衬底上流动并形成包覆成型层; 并将所述倒装芯片基板冷却至基本上低于所述模制底部填充材料的熔融温度的第三温度。 公开了一种装置。

公开(公告)号：US20130095611A1

公开(公告)日：2013-04-18

申请号：US13276143

申请日：2011-10-18

Applicant: Kuei-Wei Huang ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Kuei-Wei Huang ,  Wei-Hung Lin ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/56

Abstract: Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

Abstract translation: 公开了半导体器件的封装方法。 在一个实施例中，封装半导体器件的方法包括提供包括多个封装衬底的工件。 在多个包装基板之间移除一部分工件。 模具附接到多个封装基板中的每一个。

公开(公告)号：US20130089952A1

公开(公告)日：2013-04-11

申请号：US13270890

申请日：2011-10-11

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Chung-Shi Liu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Wei-Hung Lin ,  Kuei-Wei Huang ,  Chih-Wei Lin ,  Chun-Cheng Lin ,  Chung-Shi Liu

IPC: H01L21/60 ,  H01L23/12 ,  H01L21/603

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75754 ,  H01L2224/7698 ,  H01L2224/81001 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83102 ,  H01L2224/9205 ,  H01L2224/92125 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/013

Abstract: Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.

Abstract translation: 公开了用于半导体器件的封装处理工具和封装方法。 在一个实施例中，用于半导体器件的封装处理工具包括包括框架的机械结构。 框架包括适于将多个集成电路管芯保持在其中的多个孔。 框架包括至少一个中空区域。

公开(公告)号：US20120267423A1

公开(公告)日：2012-10-25

申请号：US13089977

申请日：2011-04-19

Applicant: Kuei-Wei Huang ,  Wei-Hung Lin ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Bor-Ping Jang ,  Chung-Shi Liu

Inventor： Kuei-Wei Huang ,  Wei-Hung Lin ,  Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Bor-Ping Jang ,  Chung-Shi Liu

IPC: B23K1/20 ,  B25J15/06

CPC classification number: H01L21/6838 ,  H01L24/75

Abstract: A vacuum tip and methods for processing thin integrated circuit dies. A vacuum tip for attaching to an integrated circuit die is disclosed comprising a vacuum port configured to connect to a vacuum supply on an upper surface and having a bottom surface; and at least one vacuum hole extending through the vacuum tip and exposed at the bottom surface of the vacuum tip; wherein the vacuum tip is configured to physically contact a surface of an integrated circuit die. Methods for processing integrated circuit dies are disclosed.

Abstract translation: 真空尖端和薄集成电路管芯的处理方法。 公开了一种用于连接到集成电路管芯的真空端头，其包括被构造成连接到上表面上的具有底表面的真空源的真空端口; 以及至少一个真空孔，其延伸穿过真空尖端并暴露在真空尖端的底表面处; 其中所述真空尖端被配置为物理地接触集成电路管芯的表面。 公开了集成电路管芯的处理方法。

公开(公告)号：USD586933S1

公开(公告)日：2009-02-17

申请号：US29250336

申请日：2006-11-10

Applicant: Chun-Cheng Lin

Designer： Chun-Cheng Lin

公开(公告)号：US20090032822A1

公开(公告)日：2009-02-05

申请号：US11939552

申请日：2007-11-13

Applicant: Chun-Cheng Lin ,  Abram Chang ,  Sheng-Jia Sheu ,  Eddie Huang

Inventor： Chun-Cheng Lin ,  Abram Chang ,  Sheng-Jia Sheu ,  Eddie Huang

IPC: H01L33/00

CPC classification number: H05K1/0203 ,  H01L33/647 ,  H05K1/18 ,  H05K2201/10106 ,  H05K2201/10659

Abstract: A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin.

Abstract translation: 大功率发光二极管，大功率发光二极管包括发光二极管芯片，主模块，两个第一电极引脚，两个第二电极引脚和至少一个散热板。 主模块具有凹面，发光二极管芯片位于凹面。 第一电极引脚连接到主模块的第一侧，并且电连接到发光二极管芯片。 第二电极引脚布置在主模块的相对于第一电极引脚的第二侧，其中第二电极引脚和第一电极引脚电气相对。 第二电极引脚电连接到发光二极管芯片。 散热板与主模块的一部分连接在第一电极销和第二电极销之间。